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ADG2128 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADG2128
Beschreibung IC CMOS 8 x 12 Unbuffered Analog Switch Array
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 28 Seiten
ADG2128 Datasheet, Funktion
Data Sheet
I2C® CMOS 8 × 12 Unbuffered Analog
Switch Array With Dual/Single Supplies
ADG2128
FEATURES
I2C-compatible interface
3.4 MHz high speed I2C option
32-lead LFCSP_VQ (5 mm × 5 mm)
Double-buffered input logic
Simultaneous update of multiple switches
Up to 300 MHz bandwidth
Fully specified at dual ±5 V/single +12 V operation
On resistance 35 Ω maximum
Low quiescent current < 20 µA
Qualified for automotive applications
APPLICATIONS
AV switching in TV
Automotive infotainment
AV receivers
CCTV
Ultrasound applications
KVM switching
Telecom applications
Test equipment/instrumentation
PBX systems
GENERAL DESCRIPTION
The ADG2128 is an analog cross point switch with an
array size of 8 × 12. The switch array is arranged so that
there are eight columns by 12 rows, for a total of 96 switch
channels. The array is bidirectional, and the rows and columns
can be configured as either inputs or outputs. Each of the 96
switches can be addressed and configured through the I2C-
compatible interface. Standard, full speed, and high speed
(3.4 MHz) I2C interfaces are supported. Any simultaneous
switch combination is allowed. An additional feature of the
ADG2128 is that switches can be updated simultaneously,
using the LDSW command. In addition, a RESET option
allows all of the switch channels to be reset/off. At power-on,
all switches are in the off condition. The device is packaged
in a 32-lead, 5 mm × 5 mm LFCSP_VQ.
ADG2128
FUNCTIONAL BLOCK DIAGRAM
VDD VSS
VL
SCL
SDA
INPUT
REGISTER
AND
7 TO 96
DECODER
1
96
1
LATCHES
96
LDSW
LDSW
8 × 12 SWITCH ARRAY
A2 A1 A0
GND
Figure 1.
Y0 TO Y7 (I/O)
X0 TO X11 (I/O)
Rev. D
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ADG2128 Datasheet, Funktion
ADG2128
Parameter
Input Leakage Current, IIN
Input Hysteresis
Input Capacitance, CIN
LOGIC OUTPUT (SDA)2
Output Low Voltage, VOL
Floating State Leakage Current
POWER REQUIREMENTS
IDD
ISS
IL
Interface Inactive
Interface Active: 400 kHz fSCL
Interface Active: 3.4 MHz fSCL
B Version
−40°C to
+25°C +125°C
0.005
±1
0.05 VL
7
0.4
0.6
±1
0.05
1
0.05
1
0.3
2
0.1
0.1
0.4
0.3
Y Version
−40°C to
+25°C +125°C
0.005
±1
0.05 VL
7
0.4
0.6
±1
0.005
0.005
1
1
0.3
2
0.1
0.1
0.4
0.3
Unit
µA typ
µA max
V min
pF typ
V max
V max
µA max
µA typ
µA max
µA typ
µA max
µA typ
µA max
mA typ
mA max
mA typ
mA max
1 Temperature range is as follows: B version: –40°C to +85°C; Y version: –40°C to +125°C.
2 Guaranteed by design, not subject to production test.
Conditions
VIN = 0 V to VL
ISINK = 3 mA
ISINK = 6 mA
Digital inputs = 0 V or VL
Digital inputs = 0 V or VL
Digital inputs = 0 V or VL
-HS model only
Data Sheet
Rev. D | Page 6 of 28

6 Page









ADG2128 pdf, datenblatt
ADG2128
80
VDD = 8V
70
VSS = 0V
IDS = 10mA
60
50
TA = +85°C
TA = +125°C
40
TA = +25°C
30
TA = –40°C
20
10
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
SOURCE VOLTAGE (V)
Figure 10. RON vs. Temperature, VDD = 8 V
16
VDD = +5V
VSS = –5V
14
12
10
X CHANNELS,
VBIAS = +4V
8
6
Y CHANNELS,
VBIAS = –2V
4
2
0
0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 11. On Leakage vs. Temperature, Dual ±5 V Supplies
12
VDD = 5V
VSS = –5V
10
8
X, Y CHANNELS;
VBIAS = +4V ON X CHANNEL;
6 –2V ON Y CHANNEL
4
X, Y CHANNELS;
VBIAS = –2V ON X CHANNEL;
2 +4V ON Y CHANNEL
0
–2
0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 12. Off Leakage vs. Temperature, Dual ±5 V Supplies
Data Sheet
18
VDD = 12V
16 VSS = 0V
14
12
10
8
6
4
2
0
–2
0 20
Y CHANNELS, VBIAS = 7V
X CHANNELS, VBIAS = 7V
Y CHANNELS, VBIAS = 1V
40 60 80 100 120
TEMPERATURE (°C)
Figure 13. On Leakage vs. Temperature, 12 V Single Supply
9
VDD = 12V
8 VSS = 0V
7
6
5
4
3
2
1
0
–1
0 20
X, Y CHANNELS;
VBIAS = 7V ON X CHANNEL;
1V ON Y CHANNEL
X, Y CHANNELS;
VBIAS = 1V ON X CHANNEL;
7V ON Y CHANNEL
40 60 80 100 120
TEMPERATURE (°C)
Figure 14. Off Leakage vs. Temperature, 12 V Single Supply
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5 VDD = +5V, VSS = –5V
–4.0
–4.5
VDD = +12V, VSS = 0V
–5.0
–5 –3 –1
1
3
5
7
SUPPLY VOLTAGE (V)
9
11
Figure 15. Charge Injection vs. Supply Voltage
Rev. D | Page 12 of 28

12 Page





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