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PDF ADG1208 Data sheet ( Hoja de datos )
| Número de pieza | ADG1208 | |
| Descripción | (ADG1208 / ADG1209) iCMOS Multiplexers | |
| Fabricantes | Analog Devices | |
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Data Sheet
Low Capacitance, 4-/8-Channel,
±15 V/+12 V iCMOS Multiplexers
ADG1208/ADG1209
FEATURES
<1 pC charge injection over full signal range
1 pF off capacitance
33 V supply range
120 Ω on resistance
Fully specified at ±15 V/+12 V
3 V logic compatible inputs
Rail-to-rail operation
Break-before-make switching action
Available in a 16-lead TSSOP, a 16-lead LFCSP, and a
16-lead SOIC
Typical power consumption < 0.03 µW
APPLICATIONS
Audio and video routing
Automatic test equipment
Data-acquisition systems
Battery-powered systems
Sample-and-hold systems
Communication systems
GENERAL DESCRIPTION
The ADG1208 and ADG1209 are monolithic, iCMOS® analog
multiplexers comprising eight single channels and four differential
channels, respectively. The ADG1208 switches one of eight inputs
to a common output as determined by the 3-bit binary address
lines A0, A1, and A2. The ADG1209 switches one of four
differential inputs to a common differential output as determined
by the 2-bit binary address lines A0 and A1. An EN input on
both devices enable or disable the device. When disabled, all
channels are switched off. When on, each channel conducts
equally well in both directions and has an input signal range
that extends to the supplies.
The industrial CMOS (iCMOS) modular manufacturing
process combines high voltage complementary metal-oxide
semiconductor (CMOS) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation
of high voltage devices has been able to achieve. Unlike analog
ICs using conventional CMOS processes, iCMOS components
can tolerate high supply voltages while providing increased
performance, dramatically lower power consumption, and
reduced package size.
FUNCTIONAL BLOCK DIAGRAMS
ADG1208
ADG1209
S1 S1A
DA
S4A
D
S1B
DB
S8 S4B
1-OF-8
DECODER
1-OF-4
DECODER
A0 A1 A2 EN
A0 A1 EN
Figure 1.
The ultralow capacitance and exceptionally low charge injection
of these multiplexers make them ideal solutions for data acquisition
and sample-and-hold applications, where low glitch and fast
settling are required. Figure 2 shows that there is minimum
charge injection over the entire signal range of the device.
iCMOS construction also ensures ultralow power dissipation,
making the devices ideally suited for portable and battery-
powered instruments.
1.0
MUX (SOURCE TO DRAIN)
0.9 TA = 25°C
0.8
0.7
0.6
VDD = +15V
0.5 VSS = –15V
0.4
0.3 VDD = +12V
VSS = 0V
0.2
0.1 VDD = +5V
0 VSS = –5V
–15 –10
–5
0
5 10 15
VS (V)
Figure 2. Source to Drain Charge Injection vs. Source Voltage
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADG1208/ADG1209
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Temperature range is as follows: Y version: –40°C to +125°C.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (On)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
ADG1208
ADG1209
Channel On Leakage ID, IS (On)
ADG1208
ADG1209
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tBBM
Charge Injection
Off Isolation
Channel to Channel Crosstalk
−3 dB Bandwidth
CS (Off )
CD (Off ), ADG1208
CD (Off ), ADG1209
CD, CS (On), ADG1208
CD, CS (On), ADG1209
−40ºC to −40ºC to
+25ºC +85ºC
+125ºC Unit
300
475 567
5
16 26
60
0 to VDD
625
27
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
±0.003
±0.1
±0.003
±0.1
±0.1
±0.02
±0.2
±0.2
±0.6
±0.6
±0.6
±0.6
±0.6
±1
±1
±1
±1
±1
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
±0.001
3
2.0 V min
0.8 V max
±0.1 µA max
pF typ
100 ns typ
170 210
235
90 ns typ
110 140
160
105 ns typ
130 155
175
45 ns typ
20 ns min
−0.2 pC typ
−85 dB typ
−85 dB typ
450 MHz typ
1.2 pF typ
1.8 pF max
7.5 pF typ
9 pF max
4.5 pF typ
5.5 pF max
9 pF typ
10.5 pF max
6 pF typ
7.5 pF max
Test Conditions/Comments
VS = 0 V to 10 V, IS = −1 mA, see Figure 31
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
VS = 3 V/6 V/9 V, IS = −1 mA
VDD = 13.2 V
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32
VS = VD = 1 V or 10 V, see Figure 33
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 34
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 36
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 36
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V, see Figure 35
VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 37
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 40
RL = 50 Ω, CL = 5 pF, see Figure 39
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
Rev. E | Page 5 of 21
5 Page 
Data Sheet
ADG1208/ADG1209
VSS 1
S1A 2
S2A 3
S3A 4
ADG1209
TOP VIEW
(Not to Scale)
12 VDD
11 S1B
10 S2B
9 S3B
1. THE EXPOSED PAD IS CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER
JOINTS AND MAXIMUM THERMAL CAPABILITY,
IT IS RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SUBSTRATE, VSS.
Figure 8. 16-Lead LFCSP Pin Configuration (ADG1209)
Table 8. 16-Lead LFCSP Pin Function Descriptions (ADG1209)
Pin No. Mnemonic Description
1 VSS
Most Negative Power Supply Potential. In single-supply applications, it can be connected to ground.
2 S1A
Source Terminal 1A. Can be an input or an output.
3 S2A
Source Terminal 2A. Can be an input or an output.
4 S3A
Source Terminal 3A. Can be an input or an output.
5 S4A
Source Terminal 4A. Can be an input or an output.
6 DA
Drain Terminal A. Can be an input or an output.
7 DB
Drain Terminal B. Can be an input or an output.
8 S4B
Source Terminal 4B. Can be an input or an output.
9 S3B
Source Terminal 3B. Can be an input or an output.
10 S2B
Source Terminal 2B. Can be an input or an output.
11 S1B
Source Terminal 1B. Can be an input or an output.
12 VDD
Most Positive Power Supply Potential.
13 GND
Ground (0 V) Reference.
14 A1
Logic Control Input.
15 A0
Logic Control Input.
16 EN
Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs
determine on switches.
EPAD
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and maximum
thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 9. ADG1209 Truth Table
A1 A0
XX
00
01
10
11
EN
0
1
1
1
1
On Switch Pair
None
1
2
3
4
Rev. E | Page 11 of 21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet ADG1208.PDF ] | |
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