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ADE7768 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADE7768
Beschreibung Energy Metering IC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
ADE7768 Datasheet, Funktion
www.DataSheet4U.com
Energy Metering IC with Integrated
Oscillator and Positive Power Accumulation
ADE7768
FEATURES
On-chip oscillator as clock source
High accuracy, supports 50 Hz/60 Hz IEC62053-21
Less than 0.1% error over a dynamic range of 500 to 1
Supplies positive-only average real power on frequency
outputs F1 and F2
High frequency output CF calibrates and supplies
instantaneous, positive-only real power
Logic output REVP indicates potential miswiring or negative
power
Direct drive for electromechanical counters and 2-phase
stepper motors (F1 and F2)
Proprietary ADCs and DSPs provide high accuracy over
large variations in environmental conditions and time
On-chip power supply monitoring
On-chip creep protection (no-load threshold)
On-chip reference 2.45 V (20 ppm/°C typical) with
external overdrive capability
Single 5 V supply, low power (20 mW typical)
Low cost CMOS process
GENERAL DESCRIPTION
The ADE77681 is a high accuracy, electrical energy metering IC.
It is a pin reduction version of the ADE7755, enhanced with a
precise oscillator circuit that serves as a clock source to the chip.
The ADE7768 eliminates the cost of an external crystal or
resonator, thus reducing the overall cost of a meter built with
this IC. The chip directly interfaces with the shunt resistor.
1U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others pending.
The ADE7768 specifications surpass the accuracy require-
ments of the IEC62053-21 standard. The AN-679 Application
Note can be used as a basis for a description of an IEC61036
(equivalent to IEC62053-21) low cost, watt-hour meter
reference design.
The only analog circuitry used in the ADE7768 is in the Σ-Δ
ADCs and reference circuit. All other signal processing, such as
multiplication and filtering, is carried out in the digital domain.
This approach provides superior stability and accuracy over
time and extreme environmental conditions.
The ADE7768 supplies positive-only average real power
information on the low frequency outputs, F1 and F2. These
outputs can be used to directly drive an electromechanical
counter or interface with an MCU. The high frequency CF logic
output, ideal for calibration purposes, provides instantaneous
positive-only, real power information.
The ADE7768 includes a power supply monitoring circuit on
the VDD supply pin. The ADE7768 remains inactive until the
supply voltage on VDD reaches approximately 4 V. If the supply
falls below 4 V, the ADE7768 also remains inactive and the F1,
F2, and CF outputs are in their nonactive modes.
Internal phase matching circuitry ensures that the voltage and
current channels are phase matched, while the HPF in the
current channel eliminates dc offsets. An internal no-load
threshold ensures that the ADE7768 does not exhibit creep
when no load is present. When REVP is logic high, the
ADE7768 does not generate any pulse on F1, F2, and CF.
The ADE7768 comes in a 16-lead, narrow body SOIC package.
V2P 2
V2N 3
V1N 4
V1P 5
FUNCTIONAL BLOCK DIAGRAM
VDD
1
AGND
6
POWER
SUPPLY MONITOR
+ Σ-Δ ...110101...
ADC
ADE7768
DGND
13
MULTIPLIER
SIGNAL
PROCESSING
BLOCK
+
2.5V
REFERENCE
Σ-Δ
ADC
4kΩ
...11011001...
PHASE
CORRECTION
Φ
HPF
LPF
INTERNAL
OSCILLATOR
DIGITAL-TO-FREQUENCY
CONVERTER
7
REFIN/OUT
11
RCLKIN
8 10 9 12 14 16 15
SCF S0 S1 REVP CF F1 F2
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.






ADE7768 Datasheet, Funktion
ADE7768
TERMINOLOGY
Measurement Error
The error associated with the energy measurement made by the
ADE7768 is defined by the following formula:
Energy Registered by ADE7768 True Energy
%Error =
× 100%
True Energy
Phase Error Between Channels
The high-pass filter (HPF) in the current channel (Channel V1)
has a phase-lead response. To offset this phase response and
equalize the phase response between channels, a phase-
correction network is also placed in Channel V1. The phase-
correction network matches the phase to within 0.1° over a
range of 45 Hz to 65 Hz, and 0.2° over a range 40 Hz to 1 kHz
(see Figure 24 and Figure 25).
Power Supply Rejection (PSR)
This quantifies the ADE7768 measurement error as a
percentage of reading when the power supplies are varied.
For the ac PSR measurement, a reading at nominal supplies
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced
onto the supplies and a second reading is obtained under the
same input signal levels. Any error introduced is expressed as a
percentage of reading—see the Measurement Error definition.
For the dc PSR measurement, a reading at nominal supplies
(5 V) is taken. The supplies are then varied 5% and a second
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of the reading.
ADC Offset Error
This refers to the small dc signal (offset) associated with the
analog inputs to the ADCs. However, the HPF in Channel V1
eliminates the offset in the circuitry. Therefore, the power
calculation is not affected by this offset.
Frequency Output Error (CF)
The frequency output error of the ADE7768 is defined as the
difference between the measured output frequency (minus the
offset) and the ideal output frequency. The difference is
expressed as a percentage of the ideal frequency. The ideal
frequency is obtained from the ADE7768 transfer function.
Gain Error
The gain error of the ADE7768 is defined as the difference
between the measured output of the ADCs (minus the offset)
and the ideal output of the ADCs. The difference is expressed
as a percentage of the ideal of the ADCs.
Oscillator Frequency Tolerance
The oscillator frequency tolerance of the ADE7768 is defined as
the part-to-part frequency variation in terms of percentage at
room temperature (25°C). It is measured by taking the differ-
ence between the measured oscillator frequency and the
nominal frequency defined in the Specifications section.
Oscillator Frequency Stability
Oscillator frequency stability is defined as frequency variation
in terms of the parts-per-million drift over the operating
temperature range. In a metering application, the temperature
range is −40°C to +85°C. Oscillator frequency stability is
measured by taking the difference between the measured
oscillator frequency at −40°C and +85°C and the measured
oscillator frequency at +25°C.
Rev. A | Page 6 of 20

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ADE7768 pdf, datenblatt
ADE7768
Typical Connection Diagrams
Figure 20 shows a typical connection diagram for Channel V1.
A shunt is the current sensor selected for this example because
of its low cost compared to other current sensors, such as the
current transformer (CT). This IC is ideal for low current
meters.
RF V1P
SHUNT
±30mV
CF
V1N
RF CF
AGND
PHASE NEUTRAL
Figure 20. Typical Connection for Channel V1
Figure 21 shows a typical connection for Channel V2. Typically,
the ADE7768 is biased around the phase wire, and a resistor
divider is used to provide a voltage signal that is proportional to
the line voltage. Adjusting the ratio of RA, RB,B and RF is also a
convenient way of carrying out a gain calibration on a meter.
RA* RB
RF
V2P
CF ±165mV V2N
RF CF
NEUTRAL PHASE
*RA >> RB + RF
Figure 21. Typical Connections for Channel V2
POWER SUPPLY MONITOR
The ADE7768 contains an on-chip power supply monitor.
The power supply (VDD) is continuously monitored by the
ADE7768. If the supply is less than 4 V, the ADE7768 becomes
inactive. This is useful to ensure proper device operation at
power-up and power-down. The power supply monitor has
built-in hysteresis and filtering, which provide a high degree
of immunity to false triggering from noisy supplies.
In Figure 22, the trigger level is nominally set at 4 V. The toler-
ance on this trigger level is within ±5%. The power supply and
decoupling for the part should be such that the ripple at VDD
does not exceed 5 V ± 5%, as specified for normal operation.
HPF and Offset Effects
Figure 23 shows the effect of offsets on the real power calcula-
tion. As can be seen, offsets on Channel V1 and Channel V2
contribute a dc component after multiplication. Because this dc
component is extracted by the LPF and used to generate the real
power information, the offsets contribute a constant error to the
real power calculation. This problem is easily avoided by the
built-in HPF in Channel V1. By removing the offsets from at
least one channel, no error component can be generated at dc
by the multiplication. Error terms at the line frequency (ω) are
removed by the LPF and the digital-to-frequency conversion
(see the Digital-to-Frequency Conversion section).
Equation 6 shows how the power calculation is affected by the
dc offsets in the current and voltage channels.
{V cos (ωt ) +VOS}× {I cos (ωt ) + IOS }
(6)
=
V×I
2
+ VOS
× IOS
+ VOS
×I
cos
(ωt ) +
IOS
×V
cos
(ωt )
+ V × I × cos (2ωt )
2
VOS × IOS
V×I
2
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION
IOS × V
VOS × I
0
FREQUENCY (RAD/s)
Figure 23. Effect of Channel Offset on the Real Power Calculation
The HPF in Channel V1 has an associated phase response that
is compensated for on chip. Figure 24 and Figure 25 show the
phase error between channels with the compensation network
activated. The ADE7768 is phase compensated up to 1 kHz as
shown. This ensures correct active harmonic power calculation
even at low power factors.
0.30
0.25
VDD
5V
4V
0.20
0.15
0.10
0V
TIME
0.05
0
–0.05
INTERNAL
ACTIVATION INACTIVE
ACTIVE
INACTIVE
Figure 22. On-Chip Power Supply Monitor
–0.10
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (Hz)
Figure 24. Phase Error Between Channels (0 Hz to 1 kHz)
Rev. A | Page 12 of 20

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