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PDF ADA4899-1 Data sheet ( Hoja de datos )
| Número de pieza | ADA4899-1 | |
| Descripción | High Speed Op Amp | |
| Fabricantes | Analog Devices | |
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Unity Gain Stable, Ultralow Distortion,
1 nV/√Hz Voltage Noise, High Speed Op Amp
ADA4899-1
FEATURES
Unity gain stable
Ultralow noise: 1 nV/√Hz, 2.6 pA/√Hz
Ultralow distortion −117 dBc at 1 MHz
High speed
−3 dB bandwidth: 600 MHz (G = +1)
Slew rate: 310 V/μs
Offset voltage: 230 μV maximum
Low input bias current: 100 nA
Wide supply voltage range: 5 V to 12 V
Supply current: 14.7 mA
High performance pinout
Disable mode
APPLICATIONS
A-to-D drivers
Instrumentation
Filters
IF and baseband amplifiers
DAC buffers
Optical electronics
GENERAL DESCRIPTION
The ADA4899-1 is an ultralow noise (1 nV/√Hz) and distortion
(<−117 dBc @1 MHz) unity gain stable voltage feedback op
amp, the combination of which makes it ideal for 16-bit and
18-bit systems. The ADA4899-1 features a linear, low noise
input stage and internal compensation that achieves high slew
rates and low noise even at unity gain. ADI’s proprietary next
generation XFCB process and innovative circuit design enable
such high performance amplifiers.
The ADA4899-1 drives 100 Ω loads at breakthrough performance
levels with only 15 mA of supply current. With the wide supply
voltage range (4.5 V to 12 V), low offset voltage (230 μV
maximum), wide bandwidth (600 MHz), and slew rate
(310 V/μs), the ADA4899-1 is designed to work in the most
demanding applications. The ADA4899-1 also features an input
bias current cancellation mode, which reduces input bias
current by a factor of 60.
CONNECTION DIAGRAMS
ADA4899-1
DISABLE 1
8 +VS
FEEDBACK 2
7 VOUT
–IN 3
6 NC
+IN 4
5 –VS
NC = NO CONNECT
Figure 1. 8-Lead LFCSP_VD (CP-8-2)
ADA4899-1
FEEDBACK 1
8 DISABLE
–IN 2
+IN 3
–VS 4
7 +VS
6 VOUT
5 –VS
Figure 2. 8-Lead SOIC_N_EP (RD-8-1)
The ADA4899-1 is available in a 3 mm × 3 mm LFCSP and a
8-lead SOIC package. Both packages feature an exposed metal
paddle that improves heat transfer to the ground plane. This is a
significant improvement over traditional plastic packages. The
ADA4899-1 is rated to work over the extended industrial
temperature range, −40°C to +125°C.
–40 G = +1
–50
VS = ±5V
RL = 1kΩ
–60 VOUT = 2V p-p
–70
–80
–90
–100
HD3
HD2
–110
–120
–130
0.1
1 10
FREQUENCY (MHz)
Figure 3. Harmonic Distortion vs. Frequency
100
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
ADA4899-1
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Supply Voltage
12.6 V
Power Dissipation
See Figure 4
Differential Input Voltage
±1.2 V
Differential Input Current
±10 mA
Storage Temperature Range
–65°C to +150°C
Operating Temperature Range
–40°C to +125°C
Lead Temperature (Soldering 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4899-1
package is limited by the associated rise in junction temperature
(TJ) on the die. The plastic encapsulating the die locally reaches
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4899-1.
Exceeding a junction temperature of 150°C for an extended
period can result in changes in silicon devices, potentially
causing failure.
The still-air thermal properties of the package and PCB (θJA),
the ambient temperature (TA), and the total power dissipated in
the package (PD) determine the junction temperature of the die.
The junction temperature is calculated as
TJ = TA + (PD × θJA)
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, the total drive power is VS/2 × IOUT, some of which is
dissipated in the package and some in the load (VOUT × IOUT).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
PD = Quiescent Power + (Total Drive Power – Load Power)
( )PD =
VS × IS
+
⎜⎜⎝⎛
VS
2
× VOUT
RL
⎟⎟⎠⎞ –
VOUT 2
RL
RMS output voltages should be considered. If RL is referenced to
VS–, as in single-supply operation, then the total drive power is
VS × IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply:
PD
= (VS
×IS )+
(VS / 4)2
RL
In single-supply operation with RL referenced to VS–, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA. Soldering the exposed paddle to the ground
plane significantly reduces the overall thermal resistance of the
package.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
(e-pad) SOIC-8 (70°C/W) and LFCSP (70°C/W) packages on a
JEDEC standard 4-layer board. θJA values are approximations.
4.0
3.5
3.0
2.5
2.0
1.5
LFCSP AND SOIC
1.0
0.5
0.0
–40
–20
0 20 40 60 80
AMBIENT TEMPERATURE (°C)
100 120
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 20
5 Page 
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0.001
–PSR
+PSR
0.01
0.1
1
10
FREQUENCY (MHz)
100
Figure 35. Power Supply Rejection
1000
–22 VS = ±5V
DISABLE = –5V
–28
–34
–40
–46
–52
–58
–64
–70
0.1
1 10 100
FREQUENCY (MHz)
Figure 36. Off Isolation vs. Frequency
1000
N: 4653
700
MEAN: –0.083µA
SD: 0.13µA
VS = ±5V
600
500
400
300
200
100
0
–0.9 –0.6 –0.3
0
0.3 0.6
INPUT BIAS CURRENT (µA)
0.9
Figure 37. Input Bias Current Distribution
ADA4899-1
N: 4651
500 MEAN: –4.92µV
SD: 29.22µV
VS = 5V
400
300
200
100
0
–200 –150 –100 –50
0
50 100 150 200
VOLTAGE OFFSET (µV)
Figure 38. Input Offset Voltage Distribution (VS = 5 V)
N: 4655
500 MEAN: –34.62µV
SD: 28.94µV
VS = ±5V
400
300
200
100
0
–200 –150 –100 –50
0
50 100 150 200
VOLTAGE OFFSET (µV)
Figure 39. Input Offset Voltage Distribution(VS = ±5 V)
Rev. A | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
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