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83C196MH Schematic ( Datenblatt PDF ) - Intel Corporation

Teilenummer 83C196MH
Beschreibung INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Hersteller Intel Corporation
Logo Intel Corporation Logo 

Gesamt 30 Seiten
		
83C196MH Datasheet, Funktion
www.DataSheet4U.com
®
8XC196MH INDUSTRIAL MOTOR CONTROL
CHMOS MICROCONTROLLER
High Performance CHMOS 16-bit CPU
16 MHz Operating Frequency
32 Kbytes of On-chip OTPROM/ROM
744 Bytes of On-chip Register RAM
Register-to-register Architecture
16 Prioritized Interrupt Sources
Peripheral Transaction Server (PTS) with 15
Prioritized Sources
Up to 52 I/O Lines
3-phase Complementary Waveform Generator
8-channel 8- or 10-bit A/D with Sample and
Hold
2-channel UART
Event Processor Array (EPA) with 2 High-
speed Capture/Compare Modules and 4 High-
speed Compare-only Modules
Two Programmable 16-bit Timers with
Quadrature Counting Inputs
Two Pulse-width Modulator (PWM) Outputs
with High Drive Capability
Flexible 8- or 16-bit External Bus
1.75 µs 16 × 16 Multiply
3 µs 32/16 Divide
Extended Temperature Available
Idle and Powerdown Modes
Watchdog Timer
The 8XC196MH is a member of Intel’s family of 16-bit MCS® 96 microcontrollers. It is designed primarily to
control three-phase AC induction and DC brushless motors. It features an enhanced three-phase waveform
generator specifically designed for use in “inverter” motor-control applications. This peripheral provides pulse-
width modulation and three-phase sine wave generation with minimal CPU intervention. It generates three
complementary non-overlapping PWM pulses with resolutions of 0.125 µs (edge triggered) or 0.250 µs
(centered).
The 8XC196MH has two dedicated serial port peripherals, allowing less software overhead. The watchdog timer
can be programmed with one of four time options.
The 8XC196MH is available as the 80C196MH, which does not have on-chip ROM, the 87C196MH,
which contains 32 Kbytes of on-chip OTPROM* or factory programmed ROM, and the 83C196MH, which
contains 32 Kbytes of factory programmed MASK ROM. It is available in 84-lead PLCC, 80-lead Shrink EIAJ/QFP,
and 64-lead SDIP. The 64-lead package does not contain pins for the P5.1/INST and P6.7/PWM1 signals.
Operational characteristics are guaranteed over the temperature range of – 40°C to + 85°C.
*One-Time Programmable Read-Only Memory (OTPROM) is similar to EPROM but comes in an unwindowed package and
cannot be erased. It is user programmable.
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 2004
August 2004
Order Number: 272543-003






83C196MH Datasheet, Funktion
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
®
VSS
P5.0/ALE/ADV#
VPP
P5.3/RD#
P5.5/BHE#/WRH#
P5.2/WR#/WRL#
P5.7/BUSWIDTH
P4.6/AD14/PBUS.14
P4.5/AD13/PBUS.13
P4.7/AD15/PBUS.15
VCC
P4.4/AD12/PBUS.12
P4.3/AD11/PBUS.11
P4.2/AD10/PBUS.10
P4.1/AD9/PBUS.9
P4.0/AD8/PBUS.8
P3.7/AD7/PBUS.7
P3.6/AD6/PBUS.6
P3.5/AD5/PBUS.5
P3.4/AD4/PBUS.4
P3.3/AD3/PBUS.3
P3.2/AD2/PBUS.2
P3.1/AD1/PBUS.1
P3.0/AD0/PBUS.0
RESET#
NMI
EA#
VSS
VCC
P6.5/WG3
P6.4/WG3#
P6.3/WG2
1
2
3
4
5
6
7
8
9
10
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12
13
14
15
16
17
18
19
20
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22
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25
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31
32
xx8XC196MH
TOP VIEW
(Looking down
on component side of
PC board)
64 P5.6/READY
63 P5.4/ONCE#
62 EXTINT
61 VSS
60 XTAL1
59 XTAL2
58 P6.6/PWM0
57 P2.7/SCLK1#/BCLK1
56 P2.6/COMP2/CPVER
55 P2.5/COMP1/PACT#
54 P2.4/COMP0/AINC#
53 P2.3/COMP3
52 P2.2/EPA1/PROG#
51 P2.1/SCLK0#/BCLK0/PALE#
50 P2.0/EPA0/PVER
49 P0.0/ACH0
48 P0.1/ACH1
47 P0.2/ACH2
46 P0.3/ACH3
45 P0.4/ACH4/PMODE.0
44 P0.5/ACH5/PMODE.1
43 VREF
42 ANGND
41 P0.6/ACH6/T1CLK/PMODE.2
40 P0.7/ACH7/T1DIR/PMODE.3
39 P1.0/TXD0
38 P1.1/RXD0
37 P1.2/TXD1
36 P1.3/RXD1
35 P6.0/WG1#
34 P6.1/WG1
33 P6.2/WG2#
Figure 3. 8XC196MH 64-lead Shrink DIP (SDIP) Package
A2572-01
6

6 Page







83C196MH pdf, datenblatt
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
®
PIN DESCRIPTIONS
Table 7. Signal Descriptions
Signal
Name
ACH7
ACH6
ACH5
ACH4
ACH3:0
AD15:8
AD7:0
ADV#
AINC#
ALE
ANGND
BCLK1
BCLK0
Type
Description
Multiplexed
With
I
I/O
O
I
O
GND
I
Analog Channels. These pins are analog inputs to the A/D
converter.
These pins are multiplexed with the port 0 pins. While it is
possible for the pins to function simultaneously as analog and
digital inputs, this is not recommended because reading the
port while a conversion is in process can produce unreliable
conversion results.
The ANGND and VREF pins must be connected for the A/D
converter and the multiplexed port pins to function.
Address/Data Lines. These pins provide a multiplexed
address and data bus. During the address phase of the bus
cycle, address bits 0–15 are presented on the bus and can
be latched using ALE or ADV#. During the data phase, 8- or
16-bit data is transferred.
Address Valid. This active-low output signal is asserted only
during external memory accesses.
ADV# indicates that valid address information is available on
the system address/data bus. The signal remains low while a
valid bus cycle is in progress and is returned high as soon as
the bus cycle completes.
An external latch can use the ADV# signal to demultiplex the
address from the address/data bus. Used with a decoder,
ADV# can generate chip-selects for external memory.
Auto Increment. In slave programming mode, this active-low
input signal enables the autoincrement mode. Auto increment
allows reading from or writing to sequential OTPROM
locations without requiring address transactions across the
programming bus for each read or write.
Address Latch Enable. This active-high output signal is
asserted only during external memory cycles.
ALE signals the start of an external bus cycle and indicates
that valid address information is available on the system
address/data bus. ALE differs from ADV# in that it is not
returned high until a new bus cycle is to begin.
An external latch can use ALE to demultiplex the address
from the address/data bus.
Analog Ground. Reference ground for the A/D converter
and the logic used to read port 0. ANGND must be held at
nominally the same potential as VSS.
Serial Communications Baud Clock 0 and 1. BCLK0 and 1
are alternate clock sources for the serial ports. The maximum
input frequency is FOSC/4.
P0.7/T1DIR/PMODE.3
P0.6/T1CLK/PMODE.2
P0.5/PMODE.1
P0.4/PMODE.0
P0.3:0
P4.7:0/PBUS.15:8
P3.7:0/PBUS.7:0
P5.0/ALE
P2.4/COMP0
P5.0/ADV#
P2.7/SCLK1#
P2.1/SCLK0#/PALE#
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