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PDF ADATE205 Data sheet ( Hoja de datos )
| Número de pieza | ADATE205 | |
| Descripción | Dual DCL | |
| Fabricantes | Analog Devices | |
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Hay una vista previa y un enlace de descarga de ADATE205 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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FEATURES
Driver, comparator, and active load
250 MHz toggle rate
Inhibit mode function
Dynamic clamps
Operating voltage range: −1.5 V to +6.5 V
Output voltage swing: 200 mV to 8 V
Four range adjustable slew rate
True/complement data mode bit
100-lead thin quad flat package, exposed pad
Low per channel power
1.15 W with load off
1.50 W with load programmed at 20 mA nominal
Low leakage (<10 nA) in High-Z mode
Driver
50 Ω output resistance
1.6 ns minimum pulse width for a 3 V step
Load: −35 mA to +35 mA maximum current range
APPLICATIONS
Automatic test equipment
Semiconductor test systems
Board test systems
Instrumentation and characterization equipment
GENERAL DESCRIPTION
The ADATE205 is a complete, single-chip solution that
performs the pin electronics functions of driver, comparator,
and active load (DCL) for ATE applications. The active load can
be powered down if not used.
The driver is a proprietary design that features three active
modes: data high mode, data low mode, and term mode, as well
as an inhibit state.
The driver has low leakage (<10 nA) in High-Z mode. The
output voltage range is −1.5 V to +6.5 V to accommodate a wide
variety of test devices.
The ADATE205 supports four programmable Tr/Tf times for
applications where slower edge rates are required. The edge rate
selection is done via two static digital CMOS select bits. The
input data to the driver can be inverted using a single CMOS
logic bit. This feature can be used for system calibration or
applications where complement input data is needed.
250 MHz Dual DCL
ADATE205
FUNCTIONAL BLOCK DIAGRAM
VCC
(18, 19, 57, 58, 77, 78, 89, 98, 99)
NC
(30, 46)
SHIELDS
(80, 82, 94, 96)
7
VIT
69
8
VIL
68
9
VIH
67
6
DR_INV
70
22
DR_DATA_P
54
23
DR_DATA_P_T
53
24
DR_DATA_N_T
52
25
DR_DATA_N
51
26
DR_EN_P
50
27
DR_EN_P_T
49
28
DR_EN_N_T
48
29
DR_EN_N
47
15
VTEN
61
14
LDEN
62
LOGIC
DRIVER
ADATE205
91
CVH 85
31
COMP_H_P
45
32
COMP_H_N
44
13
CLLM
63
COMP_L_P 34
42
35
COMP_L_N
41
90
CVL
86
COMP_H
COMP_L
LOAD
LOGIC
IOL
10
CLAMPL
65
11
CLAMPH
66
81
DUT
95
1
VCOM
75
4
VIOL
72
3
VIOH
73
2
GNDREF
74
1x
IOH
TEMP SENSOR
(5 DIODES)
88 TEMP
VEE
(16, 17, 33, 43, 59, 60, 84, 87, 92)
GND
(5, 12, 20, 21, 36, 40, 55, 56, 64, 71, 76, 79, 83, 93, 97,100)
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
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ADATE205
Parameter
Settling Time to 15 mV
Settling Time to 4 mV
Rise and Fall Time Temperature Coefficient
500 mV Swing
1 V Swing
3 V Swing
5 V Swing
Overshoot and Preshoot 200 mV swing
Overshoot and Preshoot 1 V swing
Overshoot and Preshoot 3 V swing
Overshoot and Preshoot 5 V swing
Dynamic Performance, Inhibit
Delay Time, Active High to Inhibit3
Delay Time, Active Low to Inhibit3
Delay Time, Inhibit to Active High3
Delay Time, Inhibit to Active Low3
I/O Spike
CLAMPS
VCPH, VCPL Clamp Inputs
VCPH Voltage Range
VCPL Voltage Range
Input Bias Current
Absolute Accuracy VCPH, VCPL
VCPH Offset
VCPH Gain Error
VCPH Linearity Error
VCPL Offset
VCPL Gain Error
VCPL Linearity Error
COMPARATOR DC SPECIFICATIONS4
DC Input Characteristics (VOH, VOL)
Bias Current
Voltage Range
Differential Voltage
Min Typ
8
32
2
2
2
2
1
1
2
2
3.1
2.1
2.5
3.9
350
CLAMPL
−1.8
−50
−2
−100
+55
1
+10
−100
+55
1
+10
Max Unit
ns
ns
ps/°C
ps/°C
ps/°C
ps/°C
%
%
%
%
ns
ns
ns
ns
mV
6.8
CLAMPH
+50
V
V
μA
+100
mV
V/V
mV
+100
mV
V/V
mV
−10
−1.5
−8.0
+5
Rev. 0 | Page 5 of 16
+10
+6.5
+8.0
μA
V
V
Test Conditions/Comments
Terminated, VIH = 3 V,
VIL = 0.0 V, VIT = 0.0 V
Terminated, VIH = 3 V, VIL = 0.0 V,
VIT = 0.0 V
Terminated 10% to 90%,
VIH = 1.0 V, VIL = 0.0 V,
VIT = 0.0 V, 65°C to 85°C
Terminated 10% to 90%,
VIH = 2.0 V, VIL = 0.0 V,
VIT = 0.0 V, 65°C to 85°C
Unterminated 10% to 90%,
VIH = 3.0 V, VIL = 0.0 V,
VIT = 0.0 V, 65°C to 85°C
Unterminated 10% to 90%,
VIH = 5.0 V, VIL = 0.0 V,
VIT = 0.0 V, 65°C to 85°C
Terminated, VIH = 400 mV
Terminated, VIH = 2 V
Unterminated
Unterminated
Terminated, VIH = 3.0 V,
VIL = −1.0 V
VH = 3.0 V, VL = −1.0 V,
terminated 50 Ω
Terminated, VIH = 3.0 V,
VIL = −1.0 V
Terminated, VIH = 3.0 V,
VIL = −1.0 V
Terminated, VIH = 0.0 V,
VIL = 0.0 V, VIT = 0.0 V
Maximum value bias of
reference sweep = −1.8 V to
+6.8 V
Driver = INH, VCPH = 0 V
Driver = INH, relative to line
between 0 V to 4.5 V,
VCPH = −1.5 V to +6.5 V,
VCPL = −1.8 V
Driver = INH, VCPL = 0 V
Driver = INH, relative to line
between 0 V to 4.5 V,
VCPL = −1.5 V to +6.5 V,
VCPH = 6.5 V
VOH and VOL = −1.5 V to +6.5 V
5 Page 
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Pin No.
47
48
49
50
51
52
53
54
61
62
63
65
66
67
68
69
70
72
73
74
75
80, 82, 94, 96
81
85
86
88
90
91
95
ADATE205
Mnemonic
DR_EN_N_2
DR_EN_N_T_2
DR_EN_P_T_2
DR_EN_P_2
DR_DATA_N_2
DR_DATA_N_T_2
DR_DATA_P_T_2
DR_DATA_P_2
VTEN_2
LDEN_2
Description
Complement of DR_EN_P_2.
Complement of DR_EN_N_T_2.
Termination Resistors for HS Inputs. Opposite end of each 50 Ω termination resistor goes to the
appropriate signal.
High Speed Enable Inputs. Multifunction depending on status of VTEN_2 and LDEN_2. Causes driver
to enter/leave inhibit; driver to enter/leave termination mode; load to leave/enter inhibit (see
Table 4).
Complement of DR_DATA_P_2.
Complement of DR_DATA_P_T_2.
Termination Resistors for HS Inputs. Opposite end of each 50 Ω termination resistor goes to the
appropriate signal.
High Speed Data Inputs. Sets high/low state of driver output (see Table 4).
Low Speed Control Signal. When high, DR_EN_2 forces driver output to VT; otherwise, DR_EN_2
forces driver to high impedance (see Table 4).
Determines Whether LD Responds to DR_EN_2 or is Disabled (see Table 4).
CLLM_2
Comp Low Leakage Mode.
CLAMPL_2
CLAMPH_2
VIH_2
VIL_2
VIT_2
D_INV_2
VIOL_2
VIOH_2
GNDREF_2
VCOM_2
GND/SHIELDS
DUT_2
CVH_2
CVL_2
TEMP
CVL_1
CVH_1
DUT_1
Low Clamp.
High Clamp.
Driver High Voltage Reference.
Driver Low Voltage Reference.
Driver Term Voltage Reference.
Driver Invert.
Program Voltage for IOL (Source).
Program Voltage for IOH (Sink).
Reference GND for VIOL, VIOH.
Commutation Reference Voltage.
Device Ground or Pin Shield.
Output/Input Pin.
Window High Reference Level.
Window Low Reference Level.
Temperature Sense, Five Diode String, Reference to GND.
Window Low Reference Level.
Window High Reference Level.
Output/Input pin.
Rev. 0 | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADATE205.PDF ] | |
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