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GF9330 Schematic ( PDF Datasheet ) - Gennum

Teilenummer GF9330
Beschreibung High Performance HDTV/SDTV Deinterlacer
Hersteller Gennum
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Gesamt 30 Seiten
GF9330 Datasheet, Funktion
www.DataSheet4U.com
Features
• 10/8-bit progressive scan output up to 1080p60
• support for multiplexed and non-mutiplexed Y/C video
• multi-directional edge detection processing
• adaptive inter-field motion detection
• seamless interface to Gennum's GF9331 motion co-
processor
• fully configurable to support custom video modes
• 3:2 film mode operation for HDTV/SDTV inputs
• programmable noise reduction and detail enhancement
• de-interlace, pass-through and film rate down conversion
modes of operation
• seamless interface to popular ADCs and NTSC/PAL
decoders
• ability to extract HVF information from embedded TRS
• selectable rounding and clipping of output data
• selectable blanking of active video lines
• HVF output signals with programmable output video
cropping
• serial/parallel host interface
• 3.3V supply for device I/O and 2.5V for core logic
• 5V tolerant inputs
Applications
• HDTV Up/Down Converters
• Production Equipment
• Video Walls
• Projection Systems
• Plasma Displays
• LCD TVs
• Home Theatre Systems
• HD DVD Players
GF9330 High Performance
HDTV/SDTV Deinterlacer
GF9330 Data Sheet
Device Overview
The GF9330 is a 10-bit high performance VDSP engine that
performs high quality motion adaptive de-interlacing of
interlaced digital video signals. The GF9330 supports
standard definition (SDTV) and high definition (HDTV) signal
formats and clock rates up to 1080p60 with support for
arbitrary display modes.
The GF9330 uses multi-directional adaptive filters for edge
processing, an adaptive vertical motion filter and an adaptive
inter-field motion filter. The GF9330 features detail
enhancement and noise reduction capabilities. The GF9330
also supports 3:2 pull-down, static/freeze-frame detection and
compensation and film rate conversions. The GF9330 may
operate as a stand-alone de-interlacer or may be used with
the GF9331 Motion Co-processor to enable higher quality HD/
SD de-interlacing with edge and vertical motion detection. The
two devices can be configured in tandem such that the
GF9331 sends edge detection and vertical motion filter control
information to the GF9330. These control signals adaptively
switch the GF9330's internal filters on a pixel-by-pixel basis.
The GF9330 integrates all required line delays and
seamlessly interfaces to off chip SDRAMs that form the
required field delays. The device may also operate in by-pass
mode should no processing of the input signal be desired.
Ordering Information
Part Number
GF9330-CBP
Package
328 PIN BGA
Temp. Range
0oC to 70oC
Timing
Generator
Y/C
Input
Processing
Host
Interface
3:2
Pulldown
Detector
Noise
Reducer
Detail
Enhancer
Inter-field
Motion
Detector
Control bus from GF9331
Edge Adaptive
Interpolator
Vertical Motion
Adaptive Interpolator
Inter-field Motion
Adaptive Interpolator
Field Merging
Selector
External Memory Interface
Block Diagram
Output
Processing
Processed Y/C
Proprietary and Confidential 18283 - 4 June 2004
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GF9330 Datasheet, Funktion
GF9330 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Symbol
Pin Grid
S1_RAS
S1_CAS
S1_WE
S1_ADDR[13:0]
S1_DAT[47:0]
S2_CLK
S2_CS
S2_RAS
S2_CAS
S2_WE
S2_ADDR[13:0]
S2_DAT[47:0]
TDI
TMS
TCLK
TDO
VDD_CLKD
VSS_CLKD
VDD_IO
W2
W3
Y2
V3, Y4, W4, V4, Y5, W5,
V5, U5, Y6, W6, V6, U6,
Y7, W7
V7, U7, Y8, W8, V8, U8,
T8, Y9, W9, V9, U9, W10,
V10, U10, U11, V11, W11,
Y11, U12, V12, W12, Y12,
T13, U13, V13, W13, Y13,
U14, V14, W14, Y14, U15,
V15, W15, Y15, U16, V16,
W16, Y16, U17, V17, W17,
Y17, V18, W18, Y18, W19,
Y19
A12
A18
B19
B18
A19
C18, A17, B17, C17, D17,
A16, B16, C16, D16, A15,
B15, C15, D15, A14
B14, C14, D14, A13, B13,
C13, D13, E13, B12, C12,
D12, A11, B11, C11, D11,
D10, C10, B10, A10, D9,
C9, B9, A9, E8, D8, C8,
B8, A8, D7, C7, B7, A7,
D6, C6, B6, A6, D5, C5,
B5, A5, D4, C4, B4, A4,
B3, A3, B2, A2
U1
V2
V1
Y20
F5
G5
E7, E10, E15, F7, F15, J5,
J16, M16, N5, R7, R15,
T7, T10, T15
Type
Description
O Active low SDRAM row address strobe for Field Buffer 1.
O Active low SDRAM column address strobe for Field Buffer 1.
O Active low SDRAM write enable for Field Buffer 1.
O SDRAM address for Field Buffer 1.
I/O SDRAM data for Field Buffer 1.
O SDRAM bank 2 clock.
O Active low SDRAM chip select for Field Buffer 2.
O Active low SDRAM row address strobe for Field Buffer 2.
O Active low SDRAM column address strobe for Field Buffer 2.
O Active low SDRAM write enable for Field Buffer 2.
O SDRAM address for Field Buffer 2.
I/O SDRAM data for Field Buffer 2.
I JTAG data input; connect to GND if not used.
I JTAG mode select; connect to GND if not used.
I JTAG test clock; connect to GND if not used.
O JTAG data output.
NA 2.5V supply for the internal clock doubler.
NA Ground connection for the internal clock doubler.
NA 3.3V supply.
Proprietary and Confidential 18283 - 4 June 2004
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GF9330 pdf, datenblatt
3. Detailed Device Description
GF9330 Data Sheet
3.1 Supported Input Video Formats
The GF9330 supports multiple input data formats with multiplexed or separate Y/
C channels. Data is supplied to the GF9330 through the Y_IN[9:0] and the
C_IN[9:0] busses. Table 3-1: Encoding of STD[4:0] for Selecting Input Data Format
outlines the data formats that are supported according to the setting of the control
register bits STD[4:0]
NOTE: For all progressive video standards the GF9330 must be manually set to
bypass mode (MODE[2:0] = 111). See 3.5 Host Interface for details.
Table 3-1: Encoding of STD[4:0] for Selecting Input Data Format
STD
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
STD[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
Description
525i (30/1.001) component SMPTE 125M. Multiplexed YCbCr data applied to Y_IN. C_IN is set LOW.
NOTE: Input clock is 27MHz.
Reserved
525i (30/1.001) component 16x9 SMPTE 267M. Multiplexed YCbCr data applied to Y_IN. C_IN is set LOW.
NOTE: Input clock is 36MHz.
Reserved
625i (25Hz) component EBU tech. 3267E. Multiplexed YCbCr data applied to Y_IN. C_IN is set LOW.
NOTE: Input clock is 27MHz.
Reserved
625i (25Hz) component 16x9 ITU-R BT.601-5 Part B. Multiplexed YCbCr data applied to Y_IN. C_IN is set
LOW.
NOTE: Input clock is 36MHz.
Reserved
525p (60/1.001Hz) SMPTE 293M. YCbCr data stream applied to Y_IN. C_IN is set LOW.
NOTE: Input clock is 54MHz.
Reserved
Reserved
Reserved
625p (50Hz) ITU-R BT.1358. YCbCr data stream applied to Y_IN. C_IN is set LOW.
NOTE: Input clock is 54MHz.
625p (50Hz) 16 x 9 with 18MHz sampling. YCbCr data stream applied to Y_IN. C_IN is set LOW.
NOTE: Input clock is 72MHz.
Generic SD input data format with 4:1:1 sampling. YCbCr data is applied to both Y_IN and C_IN. Externally
supplied F_IN, V_IN and H_IN signals are used to synchronize the input data stream.
NOTE: Input clock is 27MHz.
Proprietary and Confidential 18283 - 4 June 2004
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