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GF9105A Schematic ( PDF Datasheet ) - Gennum

Teilenummer GF9105A
Beschreibung Component Digital Transcoder
Hersteller Gennum
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Gesamt 30 Seiten
GF9105A Datasheet, Funktion
www.DataSheet4U.com
MultiGENTM GF9105A
Component Digital Transcoder
FEATURES
• drop in replacement for the GF9105 with lower power
and increased functionality
• new mode for HVF output
• new mode for using low frequency clocks with non-
multiplexed I/O data
• optimized HOST IF control signals for ensured shared
bus compatibility
• multiple format conversions from one device
4:2:2:4 <-> 4:4:4:4
4:2:2:4 <-> R/G/B/KEY
4:2:2:4 <-> Y/U/V/KEY
Y/U/V/KEY <-> R/G/B/KEY
4:4:4:4 <-> R/G/B/KEY
4:4:4:4 <-> Y/U/V/KEY
• ITU-R-601 compliant interpolation/decimation filters
• supports both single link 4:4:4:4 (SMPTE RP174) and
dual link 4:4:4:4 (SMPTE RP175) compliant I/O
• transparent conversions between Y/U/V and R/G/B
color spaces.
• fully programmable 3X3 Color Space Converter (CSC)
• 13 bit Color Space Converter coefficients
• 13 bit KEY Channel scaling coefficient
• multiplexed and non-multiplexed I/O data
• bi-directional I/O data ports with tri-stating
• parallel HOST IF for reading and writing multiplier
coefficients and device configuration words
• single +5V power supply.
ORDERING INFORMATION
PART NUMBER
GF9105ACQQ
PACKAGE
160 Pin MQFP
DATA SHEET
DEVICE OVERVIEW
The GF9105A is a drop in replacement for the GF9105 with
lower power and increased functionality. This increased
functionality gives the user the option of having HVF output
signals and the option of using a low frequency clock when
operating with non-multiplexed input and output data. The
GF9105A is a flexible VDSP engine capable of performing a
variety of format conversions. The flexible architecture of
the GF9105A also allows the user to perform a wide range
of DSP functions that require a general 3X3 multiplier
structure and/or high performance 1:2 interpolation and 2:1
decimation filters. Device configuration is selected by
writing configuration words through an asynchronous
parallel interface (HOST IF).
The GF9105A accepts either multiplexed or non-
multiplexed input data and may produce either multiplexed
or non-multiplexed output data. External H, V and F inputs
allow for the insertion of TRS words into multiplexed output
data streams.
All interpolation and decimation filtering required for ITU-R-
601 compliant 4:2:2:4 <-> 4:4:4:4 sample rate conversions
has been integrated into the GF9105A. In addition, all input
and output offset adjustments required for transparent
conversions between the Y/U/V and R/G/B color spaces
have been included within the GF9105A.
The color space converter within the GF9105A has 13 bit
multiplier coefficients, has 13 bit output resolution,
maintains full precision throughout the 3X3 calculation and
has a true unity gain by-pass mode. Sufficient resolution is
maintained within the color space converter to ensure that
truly transparent Y/U/V <-> R/G/B conversions may be
achieved. A user programmable output clipper allows the
GF9105A to output a variety of word lengths to meet
specific system requirements.
The GF9105A is packaged in a 160 pin MQFP package,
operates from a single +5V supply.
Y/G, CB/B, CR/R, KEY OR
Y/G, CB/B, CR/R, OR Y/G
XX OR CB/B
13
13
XX OR CR/R
13
11
KEY, CB/B, CR/R OR KEY
Y/G Y/G
DEMUX
4:4:4:4
OR
4:2:2:4
CB/B
CR/R
H_BLANK
AND
INPUT
OFFSET
ADJUST
CB/B
CR/R
KEY KEY
Y/G
INT
CB/B
INT
CR/R
KEY
3X3
MATRIX
MULTIPLIER
KEY SCALER
Y/G
CB/B
CR/R
KEY
Y/G
DEC
CB/B
DEC
CR/R
Y/G
OUTPUT
OFFSET CB/B
ADJUST
CR/R
KEY KEY
Y/G
OUTPUT
CLIP
CB/B
CR/R
OUTPUT
MULTIPLEXER
KEY
13 Y/G, CB/B, CR/R, KEY OR
Y/G, CB/B, CR/R, OR Y/G
13
CB/B OR XX
13
CR/R OR XX
11
KEY OR KEY, CB/B, CR/R
GENERAL FUNCTIONALITY OF GF9105A CORE
Revision Date: March 2000
Document No. 521 - 88 - 03
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com






GF9105A Datasheet, Funktion
SL/DL_IN
BYPASS_F
MUXED_IN
GS9001 HB[1:0] IOA[1:0]
FIL_RND
RND8/10
22
MATRIX &
KEY SCALER
COEFFICIENTS
LOWF
RND8/10
OOA[1:0]
OUTPUT/INPUT
2
CLP_D[1:0] MUXED OUT 4:4:4:4/4:2:2:4_OUT
RND8/10
2
GS9001 SL/DL_OUT
S
Y/G, CB/B, CR/R, KEY
13 C1
OR Y/G, CB/B, CR/R,OR Y/G
XX OR CB/B
13 C2
XX OR CR/R
13 C3
KEY, CB/B, CR/R OR KEY
11 C4
10
DEMUX
4:4:4:4
OR
4:2:2:4
Y/G
10
CB/B
10
CR/R
Y/G
H_BLANK
AND
INPUT
OFFSET
ADJUST
CB/B
CR/R
10
KEY KEY
Y/G
INT
CB/B
INT
CR/R
KEY
3X3
MATRIX
MULTIPLIER
KEY SCALER
Y/G Y/G
CB/B
CR/R
OUTPUT
OFFSET
CB/B
ADJUST
CR/R
Y/G
OUTPUT CB/B
CLIPPING
CR/R
OUTPUT
MULTIPLEXER
KEY KEY
KEY
13
C5
C6 13
13
C7
Y/G, CB/B, CR/R,KEY OR
Y/G, CB/B, CR/R, OR Y/G
CB/B OR XX
CR/R OR XX
C8 11
KEY OR KEY, CB/B, CR/R
SYNC_CB
H_BLANK
CLOCK
DP_EN
HV F
Fig. 5a Functionality of GF9105A Processing Core when INT/DEC = 1, HVF_OUT = 0
SL/DL_IN
MUXED_IN GS9001
HB [1:0] IOA [1:0]
22
MATRIX &
KEY SCALER
COEFFICIENTS
RND8/10
BYPASS_F OOA [1:0]
LOWF RND8/10
OUTPUT/INPUT
FIL_RND
2
CLP_D [1:0]
MUXED OUT 4:4:4:4/4:2:2:4_OUT
RND8/10
2
GS9001 SL/DL_OUT
S
Y/G, CB/B, CR/R, KEY OR
Y/G, CB/B, CR/R, OR Y/G
13 C1
XX OR CB/B
XX OR CR/R
13 C2
13 C3
KEY, CB/B, CR/R OR KEY
11 C4
13
DEMUX
4:4:4:4
OR
4:2:2:4
Y/G
13
CB/B
13
CR/R
Y/G
H_BLANK
AND
INPUT
OFFSET
ADJUST
CB/B
CR/R
11
KEY KEY
3X3
MATRIX
MULTIPLIER
KEY SCALER
Y/G
CB/B
CR/R
KEY
Y/G Y/G
DEC OUTPUT
CB/B OFFSET CB/B
DEC ADJUST
CR/R CR/R
Y/G
OUTPUT
CLIPPING
CB/B
OUTPUT
MULTIPLEXER
CR/R
KEY KEY
KEY
C5 13
C6 13
C7 13
Y/G, CB/B, CR/R, KEY OR
Y/G, CB/B, CR/R, OR Y/G
CB/B OR XX
CR/R OR XX
C8 11
KEY OR KEY, CB/B, CR/R
SYNC_CB
H_BLANK
CLOCK
DP_EN
HV F
Fig. 5b Functionality of GF9105A Processing Core when INT/DEC = 0, HVF_OUT = 0
521 - 88 - 03
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GF9105A pdf, datenblatt
Single Link (SL/DL_IN = 1)
When operating with single link input data, the 4:4:4:4 data stream (SMPTE RP174 compliant) enters the GF9105A
Processing Core from Processing Core input C1.
While OUTPUT/INPUT = 0 Processing Core Port C1 corresponds to device data port P1 (refer to Figures 4a and 4c). While
OUTPUT/INPUT = 1 Processing Core Port C1 corresponds to device data port P5 (refer to Figures 4b and 4d). In this
mode, the input clock (CLK) is operating at 54 MHz. Also, note that the MUXED_IN control bit must be set low (MUXED_IN
= 0).
MUXED_IN AND SL/DL_IN CONTROL BITS
MUXED_IN
SL/DL_IN
DESCRIPTION
0 0 Input is in a dual link multiplexed format.
0 1 Input is in a single link multiplexed format.
1 XX Input is in a non-multiplexed format.
SYNCHRONIZATION
In order to properly synchronize the input de-multiplexer, the GF9105A requires a SYNC_CB control signal input. For
multiplexed input data, SYNC_CB should change from high to low at the start of an even numbered CB sample. After
synchronizing the device with the incoming data stream, SYNC_CB can remain low until re-synchronization is desired. Refer
to Figure 7a for timing of SYNC_CB with a dual link multiplexed input data stream. Refer to Figure 7b for timing of SYNC_CB
with a single link multiplexed input data signal. The timing shown may be referred to as “standard SYNC_CB timing”.
In order to simplify overall system design, the HSYNC output from the GS9001 EDH Coprocessor may be used as a
SYNC_CB signal when operated with a 4:2:2 or dual link 4:4:4:4 input signal. In this mode of operation, the 10 bit multiplexed
data entering the GF9105A must be fed from the output of the GS9001 and the GF9105A’s SYNC_CB input must be fed from
the GS9001’s HSYNC output (Refer to Figure 8a). To use this mode of operation the GF9105A’s GS9001 control bit (Refer to
Host Programming Section) must be set high. When operated with a 4:2:2 or a dual link 4:4:4:4 input signal and when the
GS9001 control bit is set high, the GS9001’s HSYNC, VSYNC, and FIELD output signals may also be used to drive the
GS9105A’s output multiplexer. Refer to the Timing Reference Signal section for information regarding this.
When dealing with single link 4:4:4:4 input or output signals “standard” SYNC_CB timing above must be used. When using
standard SYNC_CB and HVF timing, the GS9001 control must be set low. The GS9020 may be used to provide such
standard SYNC_CB timing and HVF. When operated in this manner, the 10 bit multiplexed data entering the GF9105A must
be fed from the output of the GS9020 and the GF9105A’s SYNC_CB and HVF inputs must be fed from the GS9020’s H, V, F
outputs. The same GS9020/GF9105A configuration may also be used when interfacing the GF9105A to a standard 4:2:2 or
dual link 4:4:4:4 link input signal. In this case, the GS9001 control bit must still be set low.
GS9001 CONTROL BIT
GS9001
DESCRIPTION
0 Standard SYNC_CB and H,V,F timing. Simple interface to GS9020.
1 Modified SYNC_CB and H, V, F timing. Simple interface to GS9001.
NOTE: Standard SYNC_CB and H, V, F timing must be used when receiving or generating single link 4:4:4:4 signals.
With non-multiplexed input data, SYNC_CB must change from high to low at the start of an even-numbered CB sample. It is
important to note that SYNC_CB changes from high to low on an even-numbered CB sample and not an odd-numbered
sample. After synchronizing the device with the incoming data stream, the SYNC_CB signal can remain low until re-
synchronization is desired. Refer to Figure 7c for timing of SYNC_CB with non-multiplexed input data. Following the input de-
multiplexer, data is passed to the Horizontal Blanking section of the device.
HORIZONTAL BLANKING
When H_BLANK is high, all four channels of input are forced to a user selectable set of levels. When H_BLANK is low data is
passed through the Horizontal Blanking section of the device unmodified. Refer to Figures 10a and 10b for typical timing of
H_BLANK with multiplexed input data and Figure 10c for typical timing with non-multiplexed input data. In these figures, a
521 - 88 - 03
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