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GF9101 Schematic ( PDF Datasheet ) - Gennum

Teilenummer GF9101
Beschreibung High Performance Multirate Digital Filter
Hersteller Gennum
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Gesamt 23 Seiten
GF9101 Datasheet, Funktion
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MultiGEN GF9101 High
Performance Multirate Digital Filter
FEATURES
• highly optimized & flexible architecture for multirate
FIR filtering applications
• implements dual 12 tap filters operating at 40 MHz or
single 23 or 24 tap filter operating at 20 MHz maximum
data rate
• stores up to 108 fully-programmable 12 tap filters with
12 bit coefficients at each tap, dynamically
addressable in each clock cycle
• 3 flexible memory loading modes
• 20 bit pipeline for cascading up to 3 devices
• 20 bit output accumulator
• filter output negate and zero controls
• supports both symmetrical and asymmetrical FIR
filters
• 40 MHz maximum computation and input/output data
rates
DESCRIPTION
DATA SHEET
The GF9101 is a high performance multirate digital filter
which can be programmed to implement a wide range of
signal processing functions using both symmetrical and
asymmetrical filter structures. It is composed of a 12-tap
FIR filter with internal RAM to hold up to 108 individual
filters. An externally controlled address bus selects one of
the 108 filters in each clock cycle. Pipelined architecture
allows cascading of up to three devices with no additional
hardware.
Two 10-bit input shift registers are provided for multiplexed
filtering applications. The 12-bit coefficients can be
programmed in serial, high speed parallel or
microprocessor modes. In the high speed parallel mode,
any one of the 108 filters can be reprogrammed in 18 clock
cycles.
ORDERING INFORMATION
APPLICATIONS
Video rate conversion; High performance FIR filters;
Adaptive digital filters; Video encoding; Digital modulation
PART NUMBER
GF9101 - CMQ
PACKAGE
160 pin Metal Quad
TEMPERATURE
0° to 70°C
+10
DATA–A–IN
ENA
+10
DATA–B–OUT
ENB
R
R
SEL–A/B
ENC
R
R
COEF–ADDR R
1
0
TAP TAP
CELL CELL
12
7
TAP
CELL
11
7
+10
DATA–A–OUT
+10
TAP DATA–B–IN
CELL
12
ZERO
NEGATE
R
R
Σ
±14.11
4R
±13.6 TRUNCATED
DELAY
1,3,4,5
2
R DELAY SEL
±13.6
CONFIGURATION
REGISTER
DATA B SEL
PIPELINE–IN
±13.6
CARRY
IN
±13.6
R
±13.6
0+
1 ±13.6
R
±13.6
PIPELINE–OUT
Revision Date: July 1999
FB–SEL R
BLOCK DIAGRAM
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
Document No. 520 - 64 - 7






GF9101 Datasheet, Funktion
need to be loaded into the internal RAM. If location 0 is
used for filtering, MB0 > MB5 must be loaded for this
location. The example shown in Figure 2 loads the value
BBH into TEMP_REG_A.
LOAD_EN
COEF-WR
COEF_DATA
(7-0)
BBH
COEF_ADDR
(9-0)
300H
Fig. 2 Microprocessor Loading Timing Diagram
TABLE 6: Serial Mode Loading Order
Memory Bank 0
Memory Bank 1
TAP 2
TAP 1
1,2,3 .... 12 13 ........ 24
0,1,2 .... 11 0 .......... 11
25 .................................. 48
0 .......... 11 0 .......... 11
TAP4
TAP 3
2593 ............................. 2617
0 .......... 11 0 .......... 11
2618 ............................. 2642
0 .......... 11 0 .......... 11
SERIAL LOADING
Serial loading is sequential and synchronous. If serial
loading is selected the GF9101 will not enter the run mode
until the entire serial load sequence is completed at which
time the S_LOAD_CMP signal will go high. A bit will be
written each time LOAD_EN is low and COEF_WR makes a
high to low transition. Once the GF9101 is configured for
serial loading, 24 x 108 x 6 =15552 bits must be written
before the run mode is entered automatically. The 15552
bits must be entered in the order defined in Table 6. MB0 is
loaded first from RAM location 0 starting to fill the first 12
bits of tap 2. MB5 RAM location 107, tap 11 is loaded last.
When the serial load sequence is completed,
S_LOAD_CMP will go high and the run mode will be active.
Below is a serial loading timing diagram. This example
shows the serial loading start-up sequence. Notice that the
falling edge of COEF_WR is used to register the serial data.
The frequency of COEF_WR should be 1/4 CLK_IN
frequency.
Memory Bank 5
TAP12
TAP 11
5185 ............................. 5208
0 .......... 11 0 .......... 11
5209 ............................. 5233
0 .......... 11 0 .......... 11
Ram
Location
0
1
2568 ............................. 2592
0,1,2 .... 11 0 .......... 11
5160 ............................. 5184
0 .......... 11 0 .......... 11
15528 ...........................15552
0 .......... 11 0 .......... 11
107
520 - 64 - 7
CONFIGURE
LOAD_EN
COEF_WR
COEF_DATA (7)
BIT 1
BIT 2
BIT 3
BIT 15551 BIT 15552
CLK_IN
S_LOAD_CMP
Fig. 3 Serial Mode Timing Diagram
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GF9101 pdf, datenblatt
DATA_A_IN
0 12
CLK_IN
ENA
ENB
B AB
SEL_A/B
COEF_ADDR
(6-0)
01H
00H
01H
ENC
LOAD_EN
ZERO
CONFIGURE
34 5 6
AB A B
00H 01H 00H 01H
78
9 10
A
BA
B
00H 01H
00H 01H
FB _SEL
PIPELINE _OUT
Fig. 11 Timing Diagram for a 24 Tap Asymmetric Filter
DATAAIN
A23
A22
A21
A13 A12
DATABOUT
A0 A1 A2
A10 A11
x
C0
xC1
xC2
x
C10
xC11
DATAAIN A23
A22
A21
A13 A12
DATABOUT
A0
A1
A2
A10 A11
x
C23
xC22
xC21
xC13
xC12
Σ
PIPELINED
ADDER
Σ
PIPELINED
ADDER
(A23 x C0) + (A22 x C1) + (A21 x C2) +...+(A13 x C10) + (A12 x C11)
Fig. 11a Data Flow Diagram for a 24 Tap Asymmetric Filter
(A0 x C23) + (A1 x C22) + (A2 x C21) +...+(A10 x C13) + (A11 x C12)
+
(A23 x C0) + (A22 x C1) + (A21 x C2) +...+(A13 x C10) + (A12 x C11)
Fig. 11b Data Flow Diagram for a 24 Tap Asymmetric Filter
CASCADING
In the previous section, configuration for a 24 tap filter using
only one GF9101 was shown. To realize higher order (>24)
filters, up to three GF9101's would allow a 72 tap FIR filter to
be configured without any additional hardware. In Figure
13, two GF9101's are cascaded together to obtain a 48 tap
filter. The data enters DATA_A_IN (device number 1) and
exits from DATA_B_OUT (device number 1). In device
number 2, the DATA_A_OUT bus is connected to
DATA_B_IN in order to feed the data back in to the B12
register of the same device. The contents of the
configuration register will be different for the two devices to
compensate for a three register delay introduced when two
GF9101's are cascaded to get a 48 tap filter. The
configuration register contents are shown in Table 11.
520 - 64 - 7
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