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PDF PEB2025 Data sheet ( Hoja de datos )
| Número de pieza | PEB2025 | |
| Descripción | ISDN Exchange Power Controller | |
| Fabricantes | Siemens Semiconductor | |
| Logotipo |  |
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ISDN Exchange Power Controller
(IEPC)
PEB 2025
CMOS IC
Features
q Supplies power to up to four transmission lines
q CCITT recommendations compatible for power feed at the
“S” interface
q Each line is individually powered and controlled
q Wide field of applications:
– two- and four wire transmission lines
– point-to-point configurations
– point-to-multipoint configurations
q Maximum output current programmable up to 150 mA
q Programmable switch-off characteristic by overcurrent
detection
q Automatic restart after removing overload conditions
q Status detectors for each line driver
q Microprocessor compatible interface
q Interrupt output for detection of any malfunction
q High voltage CMOS technology (60 V)
P-LCC-28-R
P-DIP-22
Type
PEB 2025-N
PEB 2025-P
Version
V 1.5
V 1.5
Ordering Code
Q67100-H6300
Q67100-H6241
Package
P-LCC-28-R (SMD)
P-DIP-22
The IEPC is an integrated power controller especially designed for feeding two- and four wire
transmission lines. The IEPC is fully compatible to the CCITT recommendations on power feed at
the “S”-interface. So the IEPC can be used in PABX/Central Office and in intelligent NT´s.
The IEPC supplies power up to four transmission lines. Each line is individually powered and
controlled via microprocessor interface. An interrupt output signals any malfunction to the
microprocessor.
The high voltage CMOS technology (60 V) ensures a wide field of applications:
– two- and four wire transmission lines
– point-to-point configurations
– point-to-multipoint configurations etc.
1 05.92
1 page  
PEB 2025
Figure 2
IEPC Architecture
Semiconductor Group
5
5 Page 
PEB 2025
Address Table
CS
0
0
0
0
1
A1
0
0
1
1
x
A0
0
1
0
1
x
Write Register
The write register is organized as shown below:
Selected Line
Line 0
Line 1
Line 2
Line 3
No access
D2i D1i D0i
D0i - D2i are bit 0 - 2 of line i
(line number i = 0 - 3)
Automatic Restart-Bit (AR)
ON/OFF-Bit (ON)
must be 0
Automatic Restart Bit: Automatic restart mode is only possible in connection with the time-
dependent-current limitation, i.e. an external capacitor must be connected between pin CLCi and
GND. If D0i is high, automatic restart mode is enabled.
D2i D1i D0i
AR enabled
0
x
1
AR disabled
0
x
0
Semiconductor Group
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet PEB2025.PDF ] | |
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