Datenblatt-pdf.com


ADN2807 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADN2807
Beschreibung Clock and Data Recovery IC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
ADN2807 Datasheet, Funktion
www.DataSheet4U.com
155/622 Mb/s Clock and Data Recovery IC
with Integrated Limiting Amp
ADN2807
FEATURES
Meets SONET requirements for jitter transfer/
generation/tolerance
Quantizer sensitivity: 4 mV typical
Adjustable slice level: ±100 mV
Patented clock recovery architecture
Loss-of-signal detect range: 3 mV to 15 mV
Single-reference clock frequency for all rates, including
15/14 (7%) wrapper rate
Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or
155.52 MHz REFCLK
REFCLK inputs: LVPECL/LVDS/LVCMOS/LVTTL compatible
(LVPECL/LVDS only at 155.52 MHz)
Optional 19.44 MHz on-chip oscillator to be used with
external crystal
Loss-of-lock indicator
Loopback mode for high speed test data
Output squelch and bypass features
Single-supply operation: 3.3 V
Low power: 540 mW typical
7 mm × 7 mm, 48-lead LFCSP
GENERAL DESCRIPTION
The ADN2807 provides the receiver functions of quantization,
signal level detect, and clock and data recovery at rates of OC-3,
OC-12, and 15/14 FEC. All SONET jitter requirements are met,
including jitter transfer, jitter generation, and jitter tolerance. All
specifications are quoted for –40°C to +85°C ambient
temperature, unless otherwise noted.
The device is intended for WDM system applications and can
be used with either an external reference clock or an on-chip
oscillator with external crystal. Both native rates and 15/14 rate
digital wrappers are supported by the ADN2807, without any
change of reference clock.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power, fiber
optic receiver.
The receiver front end signal detect circuit indicates when the
input signal level has fallen below a user adjustable threshold.
The signal detect circuit has hysteresis to prevent chatter at the
output.
APPLICATIONS
SONET OC-3/-12, SDH STM-1/-4 and, 15/14 FEC rates
WDM transponders
The ADN2807 is available in a compact 7 mm × 7 mm 48-lead
chip-scale package (LFCSP).
Regenerators/repeaters
Test equipment
Passive optical networks
FUNCTIONAL BLOCK DIAGRAM
SLICEP/N
VCC VEE
CF1 CF2
LOL
2 ADN2807
PIN
QUANTIZER
NIN
PHASE
SHIFTER
PHASE
DET.
LOOP
FILTER
LOOP
FILTER
VCO
FREQUENCY
LOCK
DETECTOR
VREF
LEVEL
DETECT
THRADJ SDOUT
DATA
RETIMING
2
DATAOUTP/N
DIVIDER
1/2/4/16
2
CLKOUTP/N
FRACTIONAL
DIVIDER
3
SEL[0..2]
2
2
/n
XTAL
OSC
REFSEL[0..1]
REFCLKP/N
XO1
XO2
REFSEL
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.






ADN2807 Datasheet, Funktion
www.DataSheet4U.com
ADN2807
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
THRADJ 1
VCC 2
VEE 3
VREF 4
PIN 5
NIN 6
SLICEP 7
SLICEN 8
VEE 9
LOL 10
XO1 11
XO2 12
PIN 1
INDICATOR
ADN2807
TOP VIEW
36 VCC
35 VCC
34 VEE
33 VEE
32 SEL0
31 NC
30 SEL1
29 VEE
28 VCC
27 VEE
26 VCC
25 CF2
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Type1
1
THRADJ
AI
2, 26, 28, Pad VCC
P
3, 9, 16, 19,
22, 27, 29, 33,
34, 42, 43, 46
VEE
P
4
VREF
AO
5 PIN AI
6 NIN AI
7
SLICEP
AI
8
SLICEN
AI
10 LOL DO
11 XO1 AO
12 XO2 AO
13
REFCLKN
DI
14
REFCLKP
DI
15
REFSEL
DI
17
TDINP
AI
18
TDINN
AI
20, 47 VCC P
21 CF1 AO
23
REFSEL1
DI
24
REFSEL0
DI
25 CF2 AO
30
SEL1
DI
31 NC
32
SEL0
DI
35, 36 VCC P
37 DATAOUTN DO
38 DATAOUTP DO
39 SQUELCH DI
40 CLKOUTN DO
41 CLKOUTP DO
44
BYPASS
DI
45
SDOUT
DO
48
LOOPEN
DI
Figure 2. Pin Configuration
Description
LOS Threshold Setting Resistor.
Analog Supply.
Ground.
Internal VREF Voltage. Decouple to GND with a 0.1 µF capacitor.
Differential Data Input.
Differential Data Input.
Differential Slice Level Adjust Input.
Differential Slice Level Adjust Input.
Loss-of-Lock Indicator. LVTTL active high.
Crystal Oscillator.
Crystal Oscillator.
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
Reference Source Select. 0 = on-chip oscillator with external crystal. 1 = external clock source, LVTTL.
Differential Test Data Input. CML.
Differential Test Data Input. CML.
Digital Supply.
Frequency Loop Capacitor.
Reference Frequency Select (See Table 6) LVTTL.
Reference Frequency Select (See Table 6) LVTTL.
Frequency Loop Capacitor.
Data Rate Select (See Table 5) LVTTL.
No Connect.
Data Rate Select (See Table 5) LVTTL.
Output Driver Supply.
Differential Retimed Data Output. CML.
Differential Retimed Data Output. CML.
Disable Clock and Data Outputs. Active high. LVTTL.
Differential Recovered Clock Output. CML.
Differential Recovered Clock Output. CML.
Bypass CDR Mode. Active high. LVTTL.
Loss-of-Signal Detect Output. Active high. LVTTL.
Enable Test Data Inputs. Active high. LVTTL.
1Type: P = Power, AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output
Rev. A | Page 6 of 20

6 Page









ADN2807 pdf, datenblatt
www.DataSheet4U.com
ADN2807
FUNCTIONAL DESCRIPTION
MULTIRATE CLOCK AND DATA RECOVERY
The ADN2807 recovers clock and data from serial bit streams at
OC-3, OC-12 data rates as well as the 15/14 FEC rates. The
output of the 2.5 GHz VCO is divided down in order to support
the lower data rates. The data rate is selected by the SEL[2..0]
inputs (Table 5).
Table 5. Data Rate Selection
SEL[1..0]
Rate
00 OC-12
01 OC-3
10 OC-12 FEC
11 OC-3 FEC
Frequency (MHz)
622.08
155.52
666.51
166.63
LIMITING AMPLIFIER
The limiting amplifier has differential inputs (PIN/NIN) that
are internally terminated with 50 Ω to an on-chip voltage
reference (VREF = 0.6 V typically). These inputs are normally
ac-coupled, although dc-coupling is possible as long as the input
common-mode voltage remains above 0.4 V (Figure 24 to
Figure 26 in the Applications Information section). Input offset
is factory trimmed to achieve better than 4 mV typical
sensitivity with minimal drift. The limiting amplifier can be
driven differentially or single-ended.
SLICE ADJUST
The quantizer slicing level can be offset by ±100 mV to mitigate
the effect of ASE (amplified spontaneous emission) noise by
applying a differential voltage input of ±0.8 V to SLICEP/N
inputs. If no adjustment of the slice level is needed, SLICEP/N
should be tied to VCC.
LOSS-OF-SIGNAL (LOS) DETECTOR
The receiver front end level signal detect circuit indicates when
the input signal level has fallen below a user adjustable
threshold. The threshold is set with a single external resistor
from THRADJ (Pin 1) to GND. The LOS comparator trip point
versus the resistor value is illustrated in Figure 4 (this is only
valid for SLICEP = SLICEN = VCC). If the input level to the
ADN2807 drops below the programmed LOS threshold,
SDOUT (Pin 45) will indicate the loss-of-signal condition with
a Logic 1. The LOS response time is ~300 ns by design but will
be dominated by the RC time constant in ac-coupled
applications. If the LOS detector is used, the quantizer slice
adjust pins must both be tied to VCC. This is to avoid
interaction with the LOS threshold level.
Note that it is not expected to use both LOS and slice adjust at
the same time. Systems with optical amplifiers need the slice
adjust to evade ASE. However, a loss-of-signal in an optical link
that uses optical amplifiers causes the optical amplifier output
to be full-scale noise. Under this condition, the LOS would not
detect the failure. In this case, the loss-of-lock signal indicates
the failure because the CDR circuitry is unable to lock onto a
signal that is full-scale noise.
REFERENCE CLOCK
There are three options for providing the reference frequency to
the ADN2807: differential clock, single-ended clock, or crystal
oscillator. See Figure 15 to Figure 17 for example configurations.
ADN2807
REFCLKP
BUFFER
REFCLKN
VCC
VCC
XO1
XO2
100k100k
VCC/2
CRYSTAL
OSCILLATOR
VCC
REFSEL
Figure 15. Differential REFCLK Configuration
VCC
CLK
OSC OUT
REFCLKP
REFCLKN
NC
ADN2807
BUFFER
VCC
VCC
XO1
XO2
100k100k
VCC/2
CRYSTAL
OSCILLATOR
VCC
REFSEL
Figure 16. Single-Ended REFCLK Configuration
Rev. A | Page 12 of 20

12 Page





SeitenGesamt 20 Seiten
PDF Download[ ADN2807 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
ADN2804Clock and Data Recovery ICAnalog Devices
Analog Devices
ADN28051.25 Gbps Clock and Data Recovery ICAnalog Devices
Analog Devices
ADN2806Clock and Data Recovery ICAnalog Devices
Analog Devices
ADN2807Clock and Data Recovery ICAnalog Devices
Analog Devices
ADN2809Multi-Rate to 2.7Gbps Clock and Data Recovery IC with Limiting AmplifierAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche