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AD8153 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD8153
Beschreibung Single Buffered Mux/Demux Switch
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 24 Seiten
AD8153 Datasheet, Funktion
Data Sheet
3.2 Gbps
Single Buffered Mux/Demux Switch
AD8153
FEATURES
Single lane 2:1 mux/1:2 demux
3.2 Gbps to dc data rates
Compensates over 40 inches of FR4 at 3.2 Gbps through
Two levels of input equalization, or
Four levels of output pre-emphasis
Operates with ac- or dc-coupled differential I/O
Low deterministic jitter, typically 16 ps p-p
Low random jitter, typically 500 fs rms
On-chip terminations
Unicast or bicast on 1:2 demux function
Loopback capability on all ports
3.3 V core supply
Flexible I/O supply
Low power, typically 200 mW in basic configuration1
32-lead LFCSP package
−40°C to +85°C operating temperature range
APPLICATIONS
Low cost redundancy switch
SONET OC48/SDH16 and lower data rates
Gigabit Ethernet over backplane
Fibre Channel 1.06 Gbps and 2.12 Gbps over backplane
Serial RapidIO
PCI Express Gen 1
Infiniband over backplane
GENERAL DESCRIPTION
The AD8153 is an asynchronous, protocol agnostic, single-lane
2:1 switch with three differential CML inputs and three differential
CML outputs. The AD8159, another member of the Xstream
line of products, is suitable for similar applications that require
more than one lane.
The AD8153 is optimized for NRZ signaling with data rates of
up to 3.2 Gbps per port. Each port offers two levels of input
equalization and four levels of output pre-emphasis.
The device consists of a 2:1 multiplexer and a 1:2 demultiplexer.
There are three operating modes: pin mode, serial mode, and
mixed mode. In pin mode, lane switching, equalization, and
pre-emphasis are controlled exclusively using external pins. In
serial mode, an I2C interface is used to control the device and to
FUNCTIONAL BLOCK DIAGRAM
INPUT A
RECEIVE
EQUALIZATION
EQ
TRANSMIT
PRE-EMPHASIS
INPUT B
OUTPUT A
OUTPUT B
EQ
RECEIVE
EQUALIZATION
EQ
TRANSMIT
2:1 MULTIPLEXER/
PRE-EMPHASIS 1:2 DEMULTIPLEXER
AD8153
CONTROL
LOGIC
Figure 1.
OUTPUT C
INPUT C
SEL
BICAST
LB_A
LB_B
LB_C
MODE
RESETB
EQ_A/(SCL)
EQ_B/(SDA)
EQ_C
PE_A/(I2C_A[0])
PE_B/(I2C_A[1])
PE_C/(I2C_A[2])
provide access to advanced features, such as additional pre-
emphasis settings and output disable. In mixed mode, the user
accesses the advanced features using I2C, but controls lane
switching using the external pins.
The main application of the AD8153 is to support redundancy
on both the backplane side and the line interface side of a serial
link. The device has unicast and bicast capability, so it is capable
of supporting either 1 + 1 or 1:1 redundancy.
Using a mixture of bicast and loopback modes, the AD8153 can
also be used to test high speed serial links by duplicating the
incoming data and transmitting it to the destination port and
test equipment simultaneously.
1 Two ports active with no pre-emphasis.
Rev. A
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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AD8153 Datasheet, Funktion
AD8153
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
VCC 1
VTTO 2
ONA 3
OPA 4
VTTI 5
INA 6
IPA 7
VEE 8
AD8153
TOP VIEW
(Not to Scale)
24 MODE
23 RESETB
22 SEL
21 BICAST
20 LB_A
19 LB_B
18 LB_C
17 EQ_A/(SCL)
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
1, 9, 12
VCC
2 VTTO
3 ONA
4 OPA
5 VTTI
6 INA
7 IPA
8, 32, EPAD
VEE
10 ONB
11 OPB
13 INB
14 IPB
15 EQ_C
16 EQ_B/(SDA)
17 EQ_A/(SCL)
18 LB_C
19 LB_B
20 LB_A
21 BICAST
22 SEL
23 RESETB
24 MODE
25 PE_C/(I2C_A[2])
26 PE_B/(I2C_A[1])
27 ONC
28 OPC
29 PE_A/(I2C_A[0])
30 INC
31 IPC
EPAD
NOTES
1. EPAD NEEDS TO BE ELECTRICALLY CONNECTED TO VEE.
Figure 3. Pin Configuration
Type
Power
Power
I/O
I/O
Power
I/O
I/O
Power
I/O
I/O
I/O
I/O
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
I/O
I/O
Control
I/O
I/O
Description
Positive Supply.
Output Termination Supply.
High Speed Output Complement.
High Speed Output.
Input Termination Supply.
High Speed Input Complement.
High Speed Input.
Negative Supply.
High Speed Output Complement.
High Speed Output.
High Speed Input Complement.
High Speed Input.
Port C Input Equalization Control.
Port B Input Equalization Control/(I2C Data when MODE = 1).
Port A Input Equalization Control/(I2C Clock when MODE = 1).
Port C Loopback Enable.
Port B Loopback Enable.
Port A Loopback Enable.
Bicast Enable.
A/B Select.
Configuration Registers Reset.
Configuration Mode. 1 for Serial/Mixed Mode, 0 for Pin Mode.
Port C Pre-Emphasis Control/(I2C Slave Address Bit 2 when MODE = 1).
Port B Pre-Emphasis Control/(I2C Slave Address Bit 1 when MODE = 1).
High Speed Output Complement.
High Speed Output.
Port A Pre-Emphasis Control/(I2C Slave Address Bit 0 when MODE = 1).
High Speed Input Complement.
High Speed Output.
Exposed Pad. The EPAD needs to be electrically connected to VEE.
Rev. A | Page 6 of 24

6 Page









AD8153 pdf, datenblatt
AD8153
1000
900
800
700
600
500
400
300
200
100
0
3.0 3.1 3.2 3.3 3.4 3.5
VCC (V)
Figure 29. Eye Height vs. Core Supply Voltage
3.6
Data Sheet
1000
900
800
700
600
500
400
300
200
100
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
DATA RATE (Gbps)
Figure 30. Eye Height vs. Data Rate
Rev. A | Page 12 of 24

12 Page





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