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PDF EM785830AD Data sheet ( Hoja de datos )
| Número de pieza | EM785830AD | |
| Descripción | 8-BIT MICRO-CONTROLLER | |
| Fabricantes | ELAN Microelectronics | |
| Logotipo |  |
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EM785830AD
8-BIT MICRO-CONTROLLER
Version 1.5
ELAN MICROELECTRONICS CORP.
No. 12, Innovation 1st RD., Science-Based Industrial Park
Hsin Chu City, Taiwan.
TEL: (03) 5639977
FAX: (03) 5630118
1 page  
III. Application
Communication or general product.
IV. Pin Configuration
EM785830AD
8-bit Micro-controller
SEG1
SEG0
COM3
COM2
COM1
COM0
AVDD
PLLC
AVSS
P67
ADR/P66
1
2
3
4
5
6
7
8
9
10
11
33 PC3
32 PC2/PWM2
31 PC1/PWM1
30 PC0
29 P70/INT0
28 P71/INT1
27 P72/INT2
26 P73/INT3
25 P74/SDI
24 P75/SDO
23 P76/SCK
EM78P5830DQ,
EM78P5830ADQ
EM785830ADQ
Fig.1: 44-pin QFP assignment
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
12/14/2004 (V1.4)
5 Page 
EM785830AD
8-bit Micro-controller
R5(PAGE)
A13 A12 A11 A10
0000
0001
0010
A9 A8 A7~A0
CALL
and
INTERRUPT
PAGE0 00000~003FF
PAGE1 00400~007FF
RET
RETL
RETI
PAGE2 00800~00BFF
STACK1
STACK2
STACK3
STACK4
STACK5
STACK6
STACK7
STACK8
STACK9
STACK10
STACK11
STACK12
store
ACC,R3,R5(PAGE)
restore
1 1 1 1 PAGE15 05400~057FF
Fig.3 Program counter organization
R3 (Status, Page selection)
(Status flag, Page selection bits)
7 6 5 43210
RPAGE1 RPAGE0 IOCPAGE T P Z DC C
R/W-0 R/W-0 R/W-0 R R R/W R/W R/W
Bit 0(C) : Carry flag
Bit 1(DC) : Auxiliary carry flag
Bit 2(Z) : Zero flag
Bit 3(P) : Power down bit
Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.
Bit 4(T) : Time-out bit
Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout.
EVENT
T P REMARK
WDT wake up from sleep mode
0
0
WDT time out (not sleep mode)
0
1
/RESET wake up from sleep
10
Power up
11
Low pulse on /RESET
x X x : don't care
Bit 5(IOCPAGE) : change IOC5 ~ IOCE to another page
0/1 Î IOC page0 / IOC page1
Please refer to VII.1 Operational registers for detail IOC PAGE register configuration.
Bit 6 ~ Bit 7 (RPAGE0 ~ RPAGE1) : change R5 ~ RE to another page
(RPAGE1,RPAGE0)
R page # selected
(0,0)
R page 0
(0,1)
R page 1
(1,0)
R page 2
(1,1)
R page 3
Please refer to VII.1 Operational registers for detail R PAGE register configuration.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
12/14/2004 (V1.4)
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EM785830AD.PDF ] | |
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