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EM78P5830AA Schematic ( PDF Datasheet ) - ELAN Microelectronics

Teilenummer EM78P5830AA
Beschreibung 8-BIT MICRO-CONTROLLER
Hersteller ELAN Microelectronics
Logo ELAN Microelectronics Logo 




Gesamt 30 Seiten
EM78P5830AA Datasheet, Funktion
www.DataSheet4U.com
EM785830AA
8-BIT MICRO-CONTROLLER
Version 1.6
ELAN MICROELECTRONICS CORP.
No. 12, Innovation 1st RD., Science-Based Industrial Park
Hsin Chu City, Taiwan
TEL: (03) 5639977
FAX: (03)5630118






EM78P5830AA Datasheet, Funktion
V. Functional Block Diagram
EM785830AA
8-bit Micro-controller
CPU
TIM ING
CONTROL
TIM ER
TCC
COUNTER1
COUNTER2
WDT
ROM
RAM
DATA RAM
CONTROL REGISTER
I/O PORT
SPI
PWM
10-bit A/D
Fig.2a Block diagram
XIN XOUT PLLC
Oscillator
timing control
R1(TCC)
WDT
timer
Prescaler
DATA
RAM
Control sleep
and wakeup
on I/O port
General
RAM
R4
Interrupt
control
ROM
I nst r u c t io n
register
I nst r u c t io n
decoder
DATA & Control Bus
R2
STACK
ALU
R3
R5 ACC
SPI
PWM
10-bit A/D
IOC6
R6
PORT6
IOC7
R7
PORT7
IOC9
R9
PORT9
P62~P67
P70
P73~P76
P90~P97
Fig.2b Block diagram
IOCC
RC
PORTC
PC1~PC2
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
12/1/2004 V1.6

6 Page









EM78P5830AA pdf, datenblatt
EM785830AA
8-bit Micro-controller
Î Fsco=0.895MHz/2
If PLL is disabled, the instruction clock is 32.768kHz/2 Î Fsco=32.768kHz/2.
Bit 3 (SCES) : SPI clock edge selection bit
1ÎData shifts out on falling edge, and shifts in on rising edge. Data is hold during the high level.
0ÎData shifts out on rising edge, and shifts in on falling edge. Data is hold during the low level.
Bit 4 (SE) : SPI shift enable bit
1 Î Start to shift, and keep on 1 while the current byte is still being transmitted.
0 Î Reset as soon as the shifting is complete, and the next byte is ready to shift.
<Note> This bit has to be reset in software.
Bit 5 (SRO) : SPI read overflow bit
1 Î A new data is received while the previous data is still being hold in the SPIB register. In this situation,
the data in SPIS register will be destroyed. To avoid setting this bit, users had better to read SPIB
register even if the transmission is implemented only.
0 Î No overflow, <Note> This can only occur in slave mode.
Bit 6 (SPIE) : SPI enable bit
1 Î Enable SPI mode
0 Î Disable SPI mode
Bit 7 (RBF) : SPI read buffer full flag
1 Î Receive is finished, SPIB is full.
0 Î Receive is not finish yet, SPIB is empty.
R5 page1
Master Device
SDO
SPIR register
SPIW register
SDI
Salve Device
SPIS Reg
SDI
Bit7 Bit 0
SCK
SDO SPI module
SCK
Fig.4 Single SPI Master / Salve Communication
Fig. 4 shows how SPI to communicate with other device by SPI module. If SPI is a master controller, it
sends clock through the SCK pin. An 8-bit data is transmitted and received at the same time. If SPI,
however, is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be
shifted on a basis of both the clock rate and the selected edge.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
12/1/2004 V1.6

12 Page





SeitenGesamt 30 Seiten
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