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| Número de pieza | AN540 | |
| Descripción | Implementing IIR Digital Filters | |
| Fabricantes | Microchip Technology | |
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Implementing IIR Digital Filters
AN540
Implementing IIR Digital Filters
INTRODUCTION
This application note describes the implementation of
various digital filters using the PIC17C42, the first mem-
ber of Microchip’s 2nd generation 8-bit microcontrollers.
The PIC17C42 is a very high speed 8-bit microcontroller
with an instruction cycle time of 250ns (@ 16 MHz input
clock). Even though PIC17C42 is an 8-bit device, it’s
high speed and efficient instruction set allows imple-
mentation of digital filters for practical applications.
Traditionally digital filters are implemented using expen-
sive Digital Signal Processors (DSPs). In a system the
DSP is normally a slave processor being controlled by
either an 8- or 16-bit microcontroller. Where sampling
rates are not high (esp. in mechanical control systems),
a single chip solution is possible using the PIC17C42.
This application note provides a few examples of imple-
menting digital filters. Example code for 2nd order Infi-
nite Impulse Response (IIR) filters is given. The follow-
ing type of filters are implemented:
• Low Pass
• High Pass
• Band Pass
• Band Stop (notch) filter
This application note does not explain how to design a
filter. Filter design theory is well established and is
beyond the scope of this application note. It is assumed
that a filter is designed according to the desired specifi-
cations. The desired digital filters may be designed
using either standard techniques or using commonly
available digital filter design software packages.
Finite Impulse Response (FIR) filters have many advan-
tages over IIR filters, but are much more resource
intensive (both in terms of execution time and RAM). On
the other hand, IIR filters are quite attractive for imple-
menting with the PIC17C42 resources. Especially where
phase information is not so important, IIR filters are a
good choice (FIR filters have a linear phase response).
Of the various forms used for realizing digital filters (like,
Direct form, Direct II form, Cascade form, Parallel,
Lattice structure, etc.) the Direct II form is used in this
application note. It is easy to understand and simple
macros can be built using these structures.
THEORY OF OPERATION
Digital filters in most cases assume the following form of
relationship between the output and input sequences.
MN
y(n) = - ∑ a y(n - i) + ∑ b x(n - j)
ij
i=o j=o
The above equation basically states that the present
output is a weighted sum of the past inputs and past
outputs. In case of FIR filters, the weighted constants
ai=0 and in case of IIR filters, at least one of the ai
constant is non zero. In case of IIR, the above formula
may be re written in terms of Z transform as:
H(z) =
Y(z)
=
X(z)
M
∑ bkZ -k
k=0
N
∑1 + k=1 akZ -k
The above equation can further be rewritten in differ-
ence equation format as follows:
MN
∑ ∑y(n) = - aiy(n - i) + bjx(n - j)
i=1 j=o
Realization of the above equation is called as the Direct
Form II structure. For example, in case of a second order
structure, M=N=2, gives the following difference equa-
tions :
d(n) = x(n) + a1d(n-1) + a2d(n-2)
y(n) = b0d(n) + b1d(n-1) + b2(d(n-2)
(1)
(2)
The above difference equations may be represented as
shown in Figure 1.
FIGURE 1 - 2ND ORDER DIRECT FORM II
STRUCTURE (TRANSPOSED)
X(n)
+
b0
Y(n)
Z -1
b1 -a1
Z -1
b2 -a2
4
© 1993 Microchip Technology Inc.
4-129
DS00540B-page 1
1 page  
Implementing IIR Digital Filters
;
MOVFP16 Dn_2,AARG
; D(n-2) = multiplier
MOVFP16 Ax2,BARG
; A2 = multiplicand
call
DblMult
; (ACCd,ACCc) = A2*D(n-2)
;
; Add product to output of 1st section
; Save result in 32 bit Accumulator
;
ADD32 DPX,ACC
;
; Compute A1*D(n-1)
;
MOVFP16 Dn_1,AARG
; AARG = D(n-2) = multiplier
MOVFP16 Ax1,BARG
; BARG = A2 = multiplicand
call
DblMult
; (ACCd,ACCc) = A1*D(n-1)
;
; Compute A1*D(n-1) + A2*D(n-2) + output of previous section
; multiplications already done, so simply perform a 32 bit add
; of previously obtained multiplication results
;
ADD32 DPX,ACC
; ACC = A1*D(n-1)+A2*D(n-2)+(output of 1st
;
;
; save the upper 16 bits of D(n) from the 32 bit accumulator
; left shift the result by 1, to adjust the decimal point after
; a Q15*Q15 multiplication
;
rlcf
ACC+B1,w
rlcf
ACC+B2,w
movwf Dn
rlcf
ACC+B3,w
; decimal adjust ( mult by 2)
movwf Dn+B1
;
; Compute B2 * [D(n) + D(n-2)]
;
if B0_EQUALS_B2
ADD16ACC Dn_2,Dn,AARG
; AARG = Dn + D(n-2) = multiplier
MOVFP16 Bx0,BARG
; BARG = A2 = multiplicand
call
DblMult
; (ACCd,ACCc) = B2*[D(n)+D(n-2)]
MOVPF32 DPX,ACC
else
MOVFP16
MOVFP16
call
MOVPF32
Bx0,BARG
Dn,AARG
DblMult
DPX,ACC
; B0*D(n)
MOVFP16 Bx2,BARG
MOVFP16 Dn_2,AARG
call
DblMult
; B2*D(n-2)
ADD32 DPX,ACC
endif
;
; Shift down D(n-1) to D(n-2) after D(n-2) usage is no longer required.
; This way in the next iteration D(n-2) is equal to the present D(n-1)
;
movfp Dn_1,AARG+B0
movpf AARG+B0,Dn_2
; Shift down D(n-1)
movfp Dn_1+B1,AARG+B1
movpf AARG+B1,Dn_2+B1
; AARG = D(n-1) = multiplier
MOVFP16 Bx1,BARG
; BARG = B1 = multiplicand
call
DblMult
; (ACCd,ACCc) = B1*D(n-1)
;
; Compute Output Y = B1*D(n-1) + B2*D(n-2) + B0*D(n)
; = B1*D(n-1) + B0*[D(n) + D(n-2)]
; Since all multiplications are already done, simply perform a
; 32 bit addition
;
ADD32 DPX,ACC
; ACC = B1*D(n-1) + B2*D(n-2) + B0*D(n)
© 1993 Microchip Technology Inc.
4-133
DS00540B-page 5
4
5 Page 
Implementing IIR Digital Filters
0058 7C22
0059 5C24
005A 7D23
005B 5D25
005C 7E32
005D 7F33
005E E0AF
005F 6018
0060 0F44
0061 6019
0062 1145
0063 601A
0064 1146
0065 601B
0066 1147
0067 6020
0068 0122
0069 6021
006A 0123
006B 7C2A
006C 7D2B
006E 7F39
006F E0AF
0070 6018
0071 0F44
0072 6019
0073 1145
0074 601A
0075 1146
0076 601B
else
MOVFP16 B10,BARG
MOVFP16 Dn1,AARG
call DblMult
; B0*D(n)
MOVPF32 DPX,ACC
MOVFP16 Bx2,BARG
MOVFP16 Dn1_2,AARG
call DblMult
; B2*D(n-2)
ADD32 DPX,ACC
endif
;
; Shift down D(n-1) to D(n-2) after D(n-2) usage is no longer required.
; This way in the next iteration D(n-2) is equal to the present D(n-1)
;
movfp Dn1_1,AARG+B0
movpf AARG+B0,Dn1_2
; Shift down D(n-1)
movfp Dn1_1+B1,AARG+B1
movpf AARG+B1,Dn1_2+B1
; AARG = D(n-1) = multiplier
MOVFP B11+B0,BARG+B0
; move B11(B0) to BARG(B0)
MOVFP B11+B1,BARG+B1
; move B11(B1) to BARG(B1)
call DblMult
; (ACCd,ACCc) = B1*D(n-1)
;
; Compute Output Y = B1*D(n-1) + B2*D(n-2) + B0*D(n)
; = B1*D(n-1) + B0*[D(n) + D(n-2)]
; Since all multiplications are already done, simply perform a
; 32 bit addition
;
MOVFP DPX+B0,WREG
; get lowest byte of DPX into w
ADDWF ACC+B0
; add lowest byte of ACC, save in ACC(B0)
MOVFP DPX+B1,WREG
; get 2nd byte of DPX into w
ADDWFC ACC+B1
; add 2nd byte of ACC, save in ACC(B1)
MOVFP DPX+B2,WREG
; get 3rd byte of DPX into w
ADDWFC ACC+B2
; add 3rd byte of ACC, save in ACC(B2)
MOVFP DPX+B3,WREG
; get 4th byte of DPX into w
ADDWFC ACC+B3
; add 4th byte of ACC, save in ACC(B3)
;
; Shift down D(n) to D(n-1) so that in the next iteration, the new
; D(n-1) is the present D(n)
;
MOVFP Dn1+B0,WREG
; get byte of Dn1 into w
MOVWF Dn1_1+B0
; move to Dn1_1(B0)
MOVFP Dn1+B1,WREG
; get byte of Dn1 into w
MOVWF Dn1_1+B1
; move to Dn1_1(B1)
;
;
; 2nd Biquad filter section
;
BIQUAD A21,A22,B20,B21,Dn2,Dn2_1,Dn2_2,2
;
; Compute A22*D(n-2)
;
MOVFP Dn2_2+B0,AARG+B0
; move Dn2_2(B0) to AARG(B0)
MOVFP Dn2_2+B1,AARG+B1
; move Dn2_2(B1) to AARG(B1) 006D 7E38
MOVFP A22+B0,BARG+B0
; move A22(B0) to BARG(B0)
MOVFP A22+B1,BARG+B1
; move A22(B1) to BARG(B1)
call DblMult
; (ACCd,ACCc) = A2*D(n-2)
;
; Add product to output of 1st section
; Save result in 32 bit Accumulator
;
MOVFP
ADDWF
MOVFP
ADDWFC
MOVFP
ADDWFC
MOVFP
DPX+B0,WREG
ACC+B0
DPX+B1,WREG
ACC+B1
DPX+B2,WREG
ACC+B2
DPX+B3,WREG
; get lowest byte of DPX into w
; add lowest byte of ACC, save in ACC(B0)
; get 2nd byte of DPX into w
; add 2nd byte of ACC, save in ACC(B1)
; get 3rd byte of DPX into w
; add 3rd byte of ACC, save in ACC(B2)
; get 4th byte of DPX into w
4
© 1993 Microchip Technology Inc.
4-139
DS00540B-page 11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AN540.PDF ] | |
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