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82C836 Schematic ( PDF Datasheet ) - Chips

Teilenummer 82C836
Beschreibung Single-Chip 386sx AT
Hersteller Chips
Logo Chips Logo 




Gesamt 30 Seiten
82C836 Datasheet, Funktion
www.DataSheet4U.com
82C836
CHIPSet
Single-Chip 386sx AT
Data Sheet
March 1993
PRELIMINARY
®






82C836 Datasheet, Funktion
s Contents
82C836 CHIPSet Data Sheet
Section 12
System Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics 16- and 20MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU to Local Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Access to AT-Bus, On-board I/O, and ROM . . . . . . . . . . . . . . . . . . . . . .
DMA Access to AT-Bus, On-board I/O, and ROM . . . . . . . . . . . . . . . . . . . . . .
DMA and AT-Bus Master Access to Local Memory . . . . . . . . . . . . . . . . . . . . .
Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Local Bus Access and Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standy Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics 25MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU to Local Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU to AT-Bus, On-Board I/O, and ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA to AT-Bus, On-Board I/O, and ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA and AT-Bus Master Access to Local Memory . . . . . . . . . . . . . . . . . . . . .
Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Local Bus Access and Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standby Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-1
12-1
12-2
12-3
12-4
12-6
12-8
12-9
12-10
12-12
12-13
12-14
12-14
12-15
12-16
12-18
12-19
12-20
12-21
12-22
12-23
Section 13
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
Section 14
Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
Appendix A
Differences Between 82C836A and 82C836B . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
viii Revision 3.0
PRELIMINARY
Chips and Technologies, Inc.

6 Page









82C836 pdf, datenblatt
Section 1
82C836 CHIPSet Introduction
The 82C836 (also known as SCATsx) is a VLSI device incorporating the motherboard
logic required to build a low-cost, highly-integrated, IBM PC/AT-compatible computer.
It is designed to be used in conjunction with other Chips and Technologies controllers
such as the 82C45X VGA Controller and the 82C710 Integrated Floppy Disk and
Multifunction Controller. When used with these devices, the 82C836 acts as the heart
of a highly integrated system significantly reducing motherboard size, component count,
and the need for many I/O channel slots.
Featu res
The 82C836 provides the following features:
80386sx control logic and clocks to
support CPU speeds of up to 25MHz
with zero (or one) wait states
A 146818-compatible Real Time Clock
with 114 bytes of CMOS RAM
Two 8237-compatible DMA controllers
Two 8259-compatible interrupt
controllers
An 8254-compatible programmable
interval timer
An 82284-compatible clock generation
and READY interface
An 82288-compatible bus controller
A DRAM refresh controller
Power management features
A DRAM controller that supports up to
16 MB of DRAM using 256kB, 1MB
or 4MB DRAMs
A memory controller that provides
shadow RAM and support of either
8-bit or 16-bit BIOS ROM
Support for fast local cache RAM via
external cache controller
Four EMS page registers (LIM EMS
4.0 and 3.2 compatible)
Interface logic for an 80387sx numeric
coprocessor
Interface logic for an 8042 keyboard
controller
Fast GATEA20 and fast CPU reset logic
Compact packaging in a single 160-pin
plastic flat pack (160 PFP).
Chips and Technologies, Inc.
PRELIMINARY
Revision 3.0 1 -1

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