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PDF PE4305 Data sheet ( Hoja de datos )
| Número de pieza | PE4305 | |
| Descripción | RF Digital Attenuator | |
| Fabricantes | Peregrine Semiconductor | |
| Logotipo |  |
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Product Description
The PE4305 is a high linearity, 5-bit RF Digital Step Attenuator
(DSA) covering a 15.5 dB attenuation range in 0.5 dB steps,
and is pin compatible with the PE430x series. This 50-ohm RF
DSA provides both parallel (latched or direct mode) and serial
CMOS control interface, operates on a single 3-volt supply and
maintains high attenuation accuracy over frequency and
temperature. It also has a unique control interface that allows
the user to select an initial attenuation state at power-up. The
PE4305 exhibits very low insertion loss and low power
consumption. This functionality is delivered in a 4x4 mm QFN
footprint.
The PE4305 is manufactured in Peregrine’s patented Ultra
Thin Silicon (UTSi®) CMOS process, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Product Specification
PE4305
50 Ω RF Digital Attenuator
5-bit, 15.5 dB, DC – 4.0 GHz
Features
• Attenuation: 0.5 dB steps to 15.5 dB
• Flexible parallel and serial programming
interfaces
• Latched or direct mode
• Unique power-up state selection
• Positive CMOS control logic
• High attenuation accuracy and linearity
over temperature and frequency
• Very low power consumption
• Single-supply operation
• 50 Ω impedance
• Pin compatible with PE430x series
• Packaged in a 20 Lead 4x4 mm QFN
Figure 1. Functional Schematic Diagram
RF Input
Switched Attenuator Array
Figure 2. Package Type
4x4mm -20 Lead QFN
RF Output
Parallel Control 6
Serial Control 3
Power-Up Control 2
Control Logic Interface
Table 1. Electrical Specifications @ +25°C, VDD = 3.0 V
Parameter
Test Conditions
Frequency
Minimum Typical
Maximum
Operation Frequency
DC
Insertion Loss2
DC - 2.2 GHz
-
Attenuation Accuracy
Any Bit or Bit
Combination
DC - 2.2 GHz
-
1 dB Compression3
1 MHz - 2.2 GHz
30
Input IP31, 2
Two-tone inputs
+18 dBm
1 MHz - 2.2 GHz
-
Return Loss
DC - 2.2 GHz
15
Switching Speed
50% control to 0.5 dB
of final value
-
Notes: 1. Device Linearity will begin to degrade below 1Mhz
2. See Max input rating in Table 2 & Figures on Pages 2 to 4 for data across frequency.
3. Note Absolute Maximum in Table 3.
1.5
-
34
52
20
-
4000
2.25
±(0.25 + 3% of atten setting)
not to exceed ± 0.4 dB
-
-
-
1
Units
MHz
dB
dB
dBm
dBm
dB
µs
Document No. 70/0159~02C │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
1 page  
PE4305
Product Specification
Figure 14. Pin Configuration (Top View)
C16
RF1
Data
Clock
LE
1
2
3
4
5
20-lead QFN
4x4mm
Exposed Solder Pad
15 C8
14 RF2
13 P/S
12 Vss/GND
11 GND
Table 2. Pin Descriptions
Pin No. Pin Name
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Paddle
N/C
RF1
Data
Clock
LE
VDD
N/C
PUP2
VDD
GND
GND
Vss/GND
P/S
RF2
C8
C4
C2
GND
C1
C0.5
GND
No connect. Can be connected to any
bias.
RF port (Note 1).
Serial interface data input (Note 4).
Serial interface clock input.
Latch Enable input (Note 2).
Power supply pin.
No connect. Can be connected to any
bias.
Power-up selection bit.
Power supply pin.
Ground connection.
Ground connection.
Negative supply voltage or GND
connection(Note 3)
Parallel/Serial mode select.
RF port (Note 1).
Attenuation control bit, 8 dB.
Attenuation control bit, 4 dB.
Attenuation control bit, 2 dB.
Ground connection.
Attenuation control bit, 1 dB.
Attenuation control bit, 0.5 dB.
Ground for proper operation
Note 1: Both RF ports must be held at 0 VDC or DC blocked with an
external series capacitor.
2: Latch Enable (LE) has an internal 100 kΩ resistor to VDD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to VSS (-VDD) to bypass and disable
internal negative voltage generator.
4. Place a 10 kΩ resistor in series, as close to pin as possible to
avoid frequency resonance. See “Resistor on Pin 3” paragraph.
Document No. 70/0159~02C │ www.psemi.com
Table 3. Absolute Maximum Ratings
Symbol
VDD
VI
TST
TOP
PIN
VESD
Parameter/Conditions
Power supply voltage
Voltage on any input
Storage temperature range
Operating temperature
range
Input power (50 Ω)
ESD voltage (Human Body
Model)
Min Max Units
-0.3 4.0
V
-0.3
VDD+
0.3
V
-65 150
°C
-40 85
°C
24 dBm
500 V
Table 4. DC Electrical Specifications
Parameter
Min Typ Max Units
VDD Power Supply Voltage
2.7
3.0
3.3
IDD Power Supply Current
100
Digital Input High
0.7xVDD
Digital Input Low
0.3xVDD
Digital Input Leakage
1
V
µA
V
V
µA
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Switching Frequency
The PE4305 has a maximum 25 kHz switching
rate.
Resistor on Pin 3
A 10 kΩ resistor on the input to Pin 3 (see Figure
16) will eliminate package resonance between the
RF input pin and the digital input. Specified
attenuation error versus frequency performance is
dependent upon this condition.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
5 Page 
PE4305
Product Specification
Sales Offices
United States
Peregrine Semiconductor Corp.
9450 Carroll Park Drive
San Diego, CA 92121
Tel 1-858-731-9400
Fax 1-858-731-9499
Europe
Peregrine Semiconductor Europe
Bâtiment Maine
13-15 rue des Quatre Vents
F- 92380 Garches, France
Tel: 011- 33-1-47-41-91-73
Fax : 011-33-1-47-41-91-73
Japan
Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower
1-1-1 Uchisaiwaicho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: 011-81-3-3502-5211
Fax: 011-81-3-3502-5213
China
Peregrine Semiconductor
28G, Times Square,
No. 500 Zhangyang Road,
Shanghai, 200122, P.R. China
Tel: 011-86-21-5836-8276
Fax: 011-86-21-5836-7652
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS is a trademark of Peregrine Semiconductor
Corp.
Document No. 70/0159~02C │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet PE4305.PDF ] | |
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