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PE4302 Schematic ( PDF Datasheet ) - Peregrine Semiconductor

Teilenummer PE4302
Beschreibung RF Digital Attenuator
Hersteller Peregrine Semiconductor
Logo Peregrine Semiconductor Logo 




Gesamt 11 Seiten
PE4302 Datasheet, Funktion
www.DataSheet4U.com
Product Description
The PE4302 is a high linearity, 6-bit RF Digital Step Attenuator
“DSA” covering a 31.5 dB attenuation range in 0.5 dB steps.
This 50-ohm RF DSA provides both parallel and serial CMOS
control interface operates on a single 3-volt supply and
maintains high attenuation accuracy over frequency and
temperature. It also has a unique control interface that allows
the user to select an initial attenuation state at power-up. The
PE4302 exhibits very low insertion loss and low power
consumption. This functionality is delivered in a 4x4mm QFN
footprint.
The PE4302 is manufactured in Peregrine’s patented Ultra
Thin Silicon (UTSi®) CMOS process, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Product Specification
PE4302
50 RF Digital Attenuator
6-bit, 31.5 dB, DC – 4.0 GHz
Features
Attenuation: 0.5 dB steps to 31.5 dB
Flexible parallel and serial programming
interfaces
Unique power-up state selection
Positive CMOS control logic
High attenuation accuracy and linearity
over temperature and frequency
Very low power consumption
Single-supply operation
50 impedance
Packaged in a 20 lead 4x4mm QFN
Figure 1. Functional Schematic Diagram
RF Input
Switched Attenuator Array
Figure 2. Package Type
4x4mm -20 Lead QFN
RF Output
Parallel Control 6
Serial Control 3
Power-Up Control 2
Control Logic Interface
Table 1. Electrical Specifications @ +25°C, VDD = 3.0 V
Parameter
Test Conditions
Frequency
Minimum Typical
Operation Frequency
DC
Insertion Loss2
Attenuation Accuracy
1 dB Compression3
Any Bit or Bit
Combination
DC - 2.2 GHz
DC 1.0 GHz
1.0 < 2.2 GHz
1 MHz - 2.2 GHz
-
-
30
Input IP31,2
Two-tone inputs
+18 dBm
1 MHz - 2.2 GHz
-
Return Loss
DC - 2.2 GHz
15
Switching Speed
50% control to 0.5 dB
of final value
-
Notes: 1. Device Linearity will begin to degrade below 1 Mhz
2. See Max input rating in Table 2 & Figures on Pages 2 to 4 for data across frequency.
3. Note Absolute Maximum in Table 3.
1.5
-
34
52
20
-
Maximum
4000
1.75
±(0.10 + 3% of atten setting)
±(0.15 + 5% of atten setting)
-
-
-
1
Units
MHz
dB
dB
dB
dBm
dBm
dB
µs
Document No. 70/0056~02D www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11






PE4302 Datasheet, Funktion
Programming Options
Parallel/Serial Selection
Either a parallel or serial interface can be used to
control the PE4302. The P/S bit provides this
selection, with P/S=LOW selecting the parallel
interface and P/S=HIGH selecting the serial
interface.
Parallel Mode Interface
The parallel interface consists of five CMOS-
compatible control lines that select the desired
attenuation state, as shown in Table 5.
The parallel interface timing requirements are
defined by Figure 18 (Parallel Interface Timing
Diagram), Table 9 (Parallel Interface AC
Characteristics), and switching speed (Table 1).
For latched parallel programming the Latch Enable
(LE) should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW
(per Figure 18) to latch new attenuation state into
device.
For direct parallel programming, the Latch Enable
(LE) line should be pulled HIGH. Changing
attenuation state control values will change device
state to new attenuation. Direct Mode is ideal for
manual control of the device (using hardwire,
switches, or jumpers).
Table 5. Truth Table
P/S C16 C8
C4
C2
C1
C0.5
Attenuation
State
0 0 0 0 0 0 0 Reference Loss
0000001
0.5 dB
0000010
1 dB
0000100
2 dB
0001000
4 dB
0010000
8 dB
0100000
16 dB
0 1 1 1 1 1 1 31.5 dB
Note: Not all 64 possible combinations of C0.5-C16 are shown in table
Serial Interface
The serial interface is a 6-bit serial-in, parallel-out
shift register buffered by a transparent latch. It is
controlled by three CMOS-compatible signals: Data,
PE4302
Product Specification
Clock, and Latch Enable (LE). The Data and Clock
inputs allow data to be serially entered into the shift
register, a process that is independent of the state of
the LE input.
The LE input controls the latch. When LE is HIGH,
the latch is transparent and the contents of the serial
shift register control the attenuator. When LE is
brought LOW, data in the shift register is latched.
The shift register should be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data. The timing for this operation is defined by
Figure 17 (Serial Interface Timing Diagram) and
Table 8 (Serial Interface AC Characteristics).
Power-up Control Settings
The PE4302 always assumes a specifiable
attenuation setting on power-up. This feature exists
for both the Serial and Parallel modes of operation,
and allows a known attenuation state to be
established before an initial serial or parallel control
word is provided.
When the attenuator powers up in Serial mode (P/
S=1), the six control bits are set to whatever data is
present on the six parallel data inputs (C0.5 to C16).
This allows any one of the 64 attenuation settings to
be specified as the power-up state.
When the attenuator powers up in Parallel mode (P/
S=0) with LE=0, the control bits are automatically set
to one of four possible values. These four values
are selected by the two power-up control bits, PUP1
and PUP2, as shown in Table 6 (Power-Up Truth
Table, Parallel Mode).
Table 6. Parallel PUP Truth Table
P/S LE PUP2 PUP1
Attenuation State
00
00
00
00
01
0
1
0
1
X
0
0
1
1
X
Reference Loss
8 dB
16 dB
31 dB
Defined by C0.5-C16
Note: Power up with LE=1 provides normal parallel operation with
C0.5-C16, and PUP1 and PUP2 are not active.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 11
Document No. 70/0056~02D UltraCMOS™ RFIC Solutions

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