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W946432AD Schematic ( PDF Datasheet ) - Winbond

Teilenummer W946432AD
Beschreibung DDR SDRAM
Hersteller Winbond
Logo Winbond Logo 




Gesamt 40 Seiten
W946432AD Datasheet, Funktion
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W946432AD
512K × 4 BANKS × 32 BITS DDR SDRAM
GENERAL DESCRIPTION
The W946432AD is a high-speed CMOS Double Data Rate synchronous dynamic random access
memory organized as 512K words x 4 banks x 32 bits.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at
the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for
WRITEs.
The W946432AD operates from a differential clock (CLK and CLK the crossing of CLK going HIGH
and CLK going LOW will be referred to as the postive edge of CLK). Commands (address and control
signals) are registered at every positive edge of CLK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well as to both edges of CLK.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location
and continue for a programmed number of locations in a programmed sequence. Accesses begin with
the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command are used to select the bank and row to
be accessed. The address bits registered coincident with the READ or WRITE command are used to
select the bank and the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4 or 8 locations. An
AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at
the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for
concurrent operation, thereby providing high effective bandwidth by hiding row precharge and
activation time.
FEATURES
Double-data-rate architecture; two data transfers
per clock cycle
Bidirectional, data strobe (DQS) is transmitted/
received with data, to be used in capturing data
at the receiver
DQS is edge-aligned with data for READs;
center-aligned with data for WRITEs
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transitions with CLK
transitions
Programmable DLL on or DLL off mode
Commands entered on each positive CLK edge;
data and data mask referenced to both edges of
DQS
Four internal banks for concurrent operation
Data mask (DM) for write data
Burst lengths: 2, 4, or 8
CAS Latency: 3
AUTO PRECHARGE option for each burst
access
Auto Refresh and Self Refresh Modes
15.6us Maximum Average Periodic Refresh
Interval
2.5V (SSTL_2 compatible) I/O
VDDQ = 2.5V ± 0.2V
VDD = 2.5V ± 0.2V
PRELIMINARY DATA:9/8/00
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W946432AD Datasheet, Funktion
W946432AD
AC OPERATING CONDITIONS
(0°C TA 70°C; VDDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V)
PARAMETER/CONDITION
SYMBOL
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VIL(AC)
MIN
VREF +
0.35
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
VID(AC)
VIX(AC)
0.7
0.5*VDDQ-0.2
MAX
VREF -
0.35
VDDQ + 0.6
0.5*VDDQ+0.2
UNITS
V
V
V
V
NOTES
5
7
IDD SPECIFICATIONS AND CONDITIONS
(0°C TA 70°C; VDDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V)
OPERATING CURRENT: One Bank; Active-Precharge;
tRC = tRC MIN; tCK = tCK MIN; DQ, DM and DQS inputs changing twice per
clock cyle; address and control inputs changing once per clock cycle
OPERATING CURRENT: One Bank; Active-Read-Precharge;
Burst = 2; tRC = tRC MIN; CL = 3 ; tCK = tCK MIN; IOUT= 0 mA;
Address and control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
power-down mode; CKE VIL (MAX); tCK = tCK MIN
IDLE STANDBY CURRENT: CS VIH (MIN); All banks idle;
CKE VIH (MIN); tCK = tCK MIN; Address and other control inputs
changing once per clock cycle
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
power-down mode; CKE VIL (MAX); tCK = tCK MIN
≥ ≥ACTIVE STANDBY CURRENT: CS VIH (MIN); CKE VIH (MIN);
One bank; Active-Precharge; tRC = tRAS MAX; tCK = tCK MIN; DQ,
DM and DQS inputs changing twice per clock cycle; address and
other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing once per clock
cycle; CL = 3 ; tCK = tCK MIN; IOUT = 0 mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once per clock
cycle; CL = 3 ; tCK = tCK MIN; DQ, DM and DQS inputs changing
twice per clock cycle
AUTO REFRESH CURRENT: tRC = tRFC (MIN)
SELF REFRESH CURRENT: CKE 0.2V
SYMBOL
IDD0
IDD1
IDD2P
IDD2N
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
MAX
TBD
TBD
UNITS
mA
NOTES
mA
TBD
TBD
mA
mA
TBD
TBD
mA
mA
TBD
TBD
mA
mA
TBD
TBD
mA
mA

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W946432AD pdf, datenblatt
W946432AD
Read Latency
The READ latency is the delay, in clock cycles, between the registration of a READ command and the
availability of the first piece of output data. The latency is set to 3 clocks.
If a READ command is registered at clock edge n, and the latency is 3 clocks, the data will be available
nominally coincident with clock edge n + 3.
Figure2:REQUIRED CAS LATENCIES
REQUIRED CAS LATENCIES
CK
CK
COMMAND READ
DQS
NOP
CL=3
NOP
NOP
NOP
NOP
DQ
Burst Length = 4 in the case shown
Shown with nominal tAC, tDQSCK, and tDQSQ
DON'T CARE
Operating Mode
The normal operating mode is selected by issuing a Mode Register Set command with bits A7-A10 each set
to zero, and bits A0-A6 set to the desired values. A DLL reset is inititated by issuing a Mode Register Set
command with bits A7 and A9-A10 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired
values. A Mode Register Set command issued to reset the DLL should always be followed by a Mode
Register Set command to select normal operating mode.
All other combinations of values for A7-A10 are reserved for future use and/or test modes. Test modes and
reserved states should not be used because unknown operation or incompatibility with future versions may
result.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable isrequiredduringpower-upinitialization,andupon
returning to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon
exiting Self Refresh Mode, the DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles
must occur before a READ command can be issued.
Output Drive Strength
DS0, DS1, DS2, TBD
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