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PDF W942516AH Data sheet ( Hoja de datos )
| Número de pieza | W942516AH | |
| Descripción | DDR SDRAM | |
| Fabricantes | Winbond | |
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PRELIMINARY W942516AH
4M × 4 BANKS × 16 BIT DDR SDRAM
GENERAL DESCRIPTION
W942516AH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM), organized as 4,194,304 words × 4 banks × 16 bits. Using pipelined architecture and 0.175
µm process technology, W942516AH delivers a data bandwidth of up to 286M words per second (-7).
To fully comply with the personal computer industrial standard, W942516AH is sorted into three speed
grades: -7, -75 and -8. The -7 is compliant to the 143 MHz/CL2.5 or DDR266/CL2 specification, the -
75 is compliant to the DDR266/CL2.5 specification, the -8 is compliant to the DDR200/CL2
specification
All Inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition. And Write
and Read data are synschronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W942516AH is ideal for main memory in
high performance applications.
FEATURES
• 2.5V ± 0.2V Power Supply
• Up to 143 MHz Clock Frequency
• Double Data Rate architecture; two data transfers per clock cycle
• Differential clock inputs (CLK and CLK )
• DQS is edge-aligned with data for Read; center-aligned with data for Write
• CAS Latency: 2 and 2.5
• Burst Length: 2, 4, and 8
• Auto Refresh and Self Refresh
• Precharged Power Down and Active Power-Down
• Write Data Mask
• Write Latency = 1
• 8K Refresh cycles / 64 mS
• Interface: SSTL-2
• Packaged: TSOP II 66 pin, 400 x 875mil , 0.65mm pin pitch
KEY PARAMETERS
SYM.
DESCRIPTION
tCK Clock Cycle Time
CL=2
CL=2.5
tRAS Active to Precharge Command Period
tRC Active to Ref/Active Command Period
IDD1 Operation Current (Single bank)
IDD4 Burst Operation Current
IDD6 Self-Refresh Current
MIN.
/MAX.
min.
min.
min.
min.
max.
max.
max.
-7
7.5 nS
7 nS
45 nS
65 nS
110mA
165mA
3mA
-75
8 nS
7.5 nS
45 nS
65 nS
110mA
155mA
3mA
-8
10 nS
8 nS
50 nS
70 nS
100mA
150mA
3mA
Publication Release Date: May 2001
- 1 - Revision .0.0
1 page  
W942516AH
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Input, Output Voltage
Power Supply Voltage
Operating Temperature
Storage Temperature
Soldering Temperature (10s)
Power Dissipation
Short Circuit Output Current
SYMBOL
VIN, VOUT
VDD, VDDQ
TOPR
TSTG
TSOLDER
PD
IOUT
RATING
-0.3 ~ VDDQ +0.3
-0.3 ~ 3.6
0 ~ 70
-55 ~ 150
260
1
50
UNIT
V
V
°C
°C
°C
W
mA
NOTES
1
1
1
1
1
1
1
RECOMMENDED DC OPERATING CONDITIONS
(Ta = 0 to 70°C)
PARAMETER
SYMBOL
MIN.
TYP.
Power Supply Voltage
VDD 2.3
2.5
Power Supply Voltage (for I/O Buffer)
Input reference Voltage
VDDQ
VREF
2.3
0.49 x VDDQ
2.5
0.50 x VDDQ
Termination Voltage (System)
Input High Voltage (DC)
VTT
VIH (DC)
VREF - 0.04
VREF + 0.15
VREF
-
Input Low Voltage (DC)
VIL (DC)
-0.3
-
Differential Clock DC Input Voltage
VICK (DC)
-0.3
-
Input Differential Voltage. CLK and
CLK inputs (DC)
VID (DC)
0.36
-
Input High Voltage (AC)
VIH (AC)
VREF + 0.31
-
Input Low Voltage (AC)
Input Differential Voltage. CLK and
CLK inputs (AC)
VIL (AC)
VID (AC)
-
0.7
-
-
Differential AC input Cross Point
Voltage
VX (AC)
VDDQ/2 - 0.2
-
Differential Clock AC Middle Point
VISO (AC)
VDDQ/2 - 0.2
-
Note : Undershoot Limit : VIL(min) = -0.9V with a pulse width < 5 nS
Overshoot Limit : VIH(max) = VDDQ+0.9V with a pulse width < 5 nS
VIH(DC) and VIL(DC) are levels to maintain the current logic state.
VIH(AC) and VIL(AC) are levels to change to the new logic state.
MAX.
2.7
VDD
0.51 x VDDQ
VREF + 0.04
VDDQ + 0.3
VREF - 0.15
VDDQ + 0.3
VDDQ + 0.6
-
VREF - 0.31
VDDQ + 0.6
VDDQ/2 + 0.2
VDDQ/2 + 0.2
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
NOTES
2
2
2,3
2,8
2
2
15
13,15
2
2
13,15
12, 15
14, 15
Publication Release Date: May 2001
- 5 - Revision 0.0
5 Page 
W942516AH
Note:
(1) Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage
to the device.
(2) All voltages are referenced to VSS, VSSQ.
(3) Peak to peak AC noise on VREF may not exceed ±2% of VREF(DC).
(4) VOH=1.95V,VOL=0.35V
(5) VOH=1.9V,VOL=0.4V
(6) The values of IOH(DC) is based on VDDQ=2.3V and VTT=1.19V.
The values of IOL(DC) is based on VDDQ=2.3V and VTT=1.11V.
(7) These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimun values of
tCK and tRC.
(8) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set
equal to VREF and must track variations in the DC level of VREF.
(9) These parameters depend on the output loading.Specified values are obtained with the output open.
(10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed
slope.
(11) If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to
the nearest decimal place.
(i.e., tDQSS=0.75×tCK, tCK=7.5ns, 0.75 × 7.5ns = 5.625ns is rounded up to 5.6ns.)
(12) VX is the differential clock cross point voltage where input timing measurement is referenced.
(13) VID is magnitude of the difference between CLK input level and CLK input level.
(14) VISO means {VICK(CLK) + VICK( CLK )}/2.
(15) Refer to the figure below.
CLK
VX
CLK
VICK
VSS
VID(AC)
VX
VICK
VX
VICK
VX VICK
VX
VID(AC)
0 V Differential
VISO
VSS
VISO(min)
VISO(max)
(16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock.
- 11 -
Publication Release Date: May 2001
Revision 0.0
11 Page | ||
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| PDF Descargar | [ Datasheet W942516AH.PDF ] | |
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