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PDF AM29DL323D Data sheet ( Hoja de datos )
| Número de pieza | AM29DL323D | |
| Descripción | (AM29DL322D - AM29DL324D) Simultaneous Operation Flash Memory | |
| Fabricantes | AMD | |
| Logotipo |  |
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Am29DL322D/323D/324D
Data Sheet
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Publication Number 21534 Revision D Amendment +6 Issue Date June 10, 2003
1 page  
PRODUCT SELECTOR GUIDE
Part Number
Speed Option
Regulated Voltage Range: VCC = 3.0–3.6 V
Standard Voltage Range: VCC = 2.7–3.6 V
Max Access Time (ns)
CE# Access (ns)
OE# Access (ns)
BLOCK DIAGRAM
VCC
VSS
Am29DL322D/323D/324D
70R
90 120
70 90 120
70 90 120
30 40 50
OE# BYTE#
A20–A0
Upper Bank Address
RY/BY#
A20–A0
RESET#
WE#
CE#
BYTE#
WP#/ACC
DQ15–DQ0
STATE
CONTROL
&
COMMAND
REGISTER
Upper Bank
X-Decoder
Status
Control
X-Decoder
A20–A0
Lower Bank Address
Lower Bank
DQ15–DQ0
OE# BYTE#
4
Am29DL322D/323D/324D
June 10, 2003
5 Page 
this mode when addresses remain stable for tACC +
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
ICC5 in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is com-
pleted within a time of tREADY (not during Embedded
Algorithms). The system can read data tRH after the
RESET# pin returns to VIH.
ICC4 in the DC Characteristics table represents the
reset current. Also refer to AC Characteristics tables
for RESET# timing parameters and to Figure 14 for
the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
Device
Part Number
Am29DL322D
Am29DL323D
Am29DL324D
Megabits
4 Mbit
8 Mbit
16 Mbit
Table 2. Device Bank Divisions
Bank 1
Sector Sizes
Megabits
Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword
28 Mbit
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
24 Mbit
Eight 8 Kbyte/4 Kword,
thrity-one 64 Kbyte/32 Kword
16 Mbit
Bank 2
Sector Sizes
Fifty-six
64 Kbyte/32 Kword
Forty-eight
64 Kbyte/32 Kword
Thirty-two
64 Kbyte/32 Kword
10
Am29DL322D/323D/324D
June 10, 2003
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AM29DL323D.PDF ] | |
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