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PDF AM29BL802C Data sheet ( Hoja de datos )
| Número de pieza | AM29BL802C | |
| Descripción | Burst Mode Flash Memory | |
| Fabricantes | AMD | |
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Am29BL802C
Data Sheet
The following document contains information on Spansion memory products. Although the document
is marked with the name of the company that originally developed the specification, Spansion will
continue to offer these products to existing customers.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 22371 Revision C Amendment 7 Issue Date November 3, 2006
1 page  
DATA SHEET
TABLE OF CONTENTS
This page left intentionally blank. . . . . . . . . . . . . 2
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Device Bus Operations .......................................................8
Requirements for Reading Array Data Array in Asynchronous
(Non-Burst) Mode ..................................................................... 9
Requirements for Reading Array Data in Synchronous
(Burst) Mode ............................................................................. 9
Burst Suspend/Burst Resume Operations ................................ 9
IND# End of Burst Indicator .................................................... 10
Writing Commands/Command Sequences ............................ 10
Program and Erase Operation Status .................................... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 10
Output Disable Mode .............................................................. 11
Table 2. Sector Address Table ........................................................11
Autoselect Mode..................................................................... 12
Table 3. Am29BL802C Autoselect Codes (High Voltage Method) ..12
Sector Protection/Unprotection ............................................... 12
Figure 1. In-system Sector Protect/Unprotect Algorithms ............... 13
Temporary Sector Unprotect .................................................. 14
Figure 2. Temporary Sector Unprotect Operation........................... 14
Hardware Data Protection . . . . . . . . . . . . . . . . . . 14
Low VCC Write Inhibit .............................................................. 14
Write Pulse “Glitch” Protection ............................................... 14
Logical Inhibit .......................................................................... 14
Power-Up Write Inhibit ............................................................ 14
Command Definitions . . . . . . . . . . . . . . . . . . . . . 14
Reading Array Data in Non-burst Mode ................................. 14
Reading Array Data in Burst Mode ......................................... 15
Figure 3. Burst Mode Read with 40 MHz CLK, 65 ns tIACC,
18 ns tBACC Parameters.................................................................. 15
Figure 4. Burst Mode Read with 25 MHz CLK, 70 ns tIACC,
24 ns tBACC Parameters................................................................. 16
Reset Command ..................................................................... 16
Autoselect Command Sequence ............................................ 16
Program Command Sequence ............................................... 16
Unlock Bypass Command Sequence ..................................... 17
Figure 5. Program Operation .......................................................... 17
Chip Erase Command Sequence ........................................... 17
Sector Erase Command Sequence ........................................ 18
Figure 6. Erase Operation............................................................... 18
Erase Suspend/Erase Resume Commands ........................... 18
Asynchronous Mode ............................................................... 18
Burst Mode ............................................................................. 19
General ................................................................................... 19
Command Definitions ............................................................. 20
Table 4. Am29BL802C Command Definitions ................................20
Write Operation Status . . . . . . . . . . . . . . . . . . . . 21
DQ7: Data# Polling ................................................................. 21
Figure 7. Data# Polling Algorithm .................................................. 21
RY/BY#: Ready/Busy# ............................................................ 22
DQ6: Toggle Bit I .................................................................... 22
DQ2: Toggle Bit II ................................................................... 22
Reading Toggle Bits DQ6/DQ2 ............................................... 22
DQ5: Exceeded Timing Limits ................................................ 23
DQ3: Sector Erase Timer ....................................................... 23
Figure 8. Toggle Bit Algorithm........................................................ 23
Table 5. Write Operation Status ..................................................... 24
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 25
Figure 9. Maximum Negative Overshoot Waveform ...................... 25
Figure 10. Maximum Positive Overshoot Waveform...................... 25
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11. ICC1 Current vs. Time (Showing Active and Automatic
Sleep Currents) .............................................................................. 27
Figure 12. Typical ICC1 vs. Frequency ........................................... 27
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13. Test Setup..................................................................... 28
Table 6. Test Specifications ........................................................... 28
Key to Switching Waveforms .................................................. 28
Figure 14. Input Waveforms and Measurement Levels ................. 28
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15. Conventional Read Operations Timings ....................... 31
Figure 16. Burst Mode Read .......................................................... 31
Figure 17. RESET# Timings .......................................................... 32
Figure 18. Program Operation Timings.......................................... 34
Figure 19. Chip/Sector Erase Operation Timings .......................... 35
Figure 20. Data# Polling Timings (During Embedded Algorithms). 36
Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... 36
Figure 22. DQ2 vs. DQ6 for Erase and Erase
Suspend Operations .................................................................... 37
Figure 23. Temporary Sector Unprotect Timing Diagram .............. 37
Figure 24. Sector Protect/Unprotect Timing Diagram .................... 38
Figure 25. Alternate CE# Controlled Write Operation Timings ...... 40
Erase and Programming Performance . . . . . . . . 41
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 41
SSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 41
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Physical Dimensions*. . . . . . . . . . . . . . . . . . . . . . 42
SSO056—56-Pin Shrink Small Outline Package .................... 42
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 43
Revision A (June 1, 1999) ...................................................... 43
Revision A+1 (June 25, 1999) ................................................ 43
Revision B (November 29, 1999) ............................................ 43
Revision C (June 20, 2000) .................................................... 43
Revision C+1 (November 16, 2000) ....................................... 43
Revision C+2 (July 22, 2002) ................................................. 43
Revision C+3 (November 22, 2002) ....................................... 43
Revision C+4 (June 4, 2004) .................................................. 44
Revision C+5 (February 28, 2005) ......................................... 44
Revision C+6 (June 29, 2005) ................................................ 44
Revision C7 (November 3, 2006) ........................................... 44
November 3, 2006 22371C7
Am29BL802C
3
5 Page 
DATA SHEET
Requirements for Reading Array Data
Array in Asynchronous (Non-Burst) Mode
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at VIH.
Address access time (tACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (tCE) is the delay from the stable
addresses and stable CE# to valid data at the output
pins. The output enable access time is the delay from
the falling edge of OE# to valid data at the output pins
(assuming the addresses have been stable for at least
tACC–tOE time).
The internal state machine is set for reading array
data in the upon device power-up, or after a hardware
reset. This ensures that no spurious alteration of the
memory content occurs during the power transition.
No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs pro-
duce valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data in Non-burst Mode” for more
information. Refer to the AC Read Operations table for
timing specifications and to Figure 15 for the timing di-
agram. ICC1 in the DC Characteristics table represents
the active current specification for reading array data.
Requirements for Reading Array Data in
Synchronous (Burst) Mode
The device offers fast 32-word sequential burst reads
and is used to support microprocessors that implement
an instruction prefetch queue, as well as large data
transfers during system configuration.
Three additional pins—Load Burst Address (LBA#),
Burst Address Advance (BAA#), and Clock (CLK)—
allow interfacing to microprocessors and microcontrol-
lers with minimal glue logic. Burst mode read is a syn-
chronous operation tied to the rising edge of CLK. CE#,
OE#, and WE# are asynchronous (relative to CLK).
When the device is in asynchronous mode (after
power-up or RESET# pulse), any signals on the CLK,
LBA#, and BAA# inputs are ignored. The device oper-
ates as a conventional flash device, as described in the
previous section.
To enable burst mode operation, the system must issue
the Burst Mode Enable command sequence (see Table
4). After the device has entered the burst mode, the
system must assert Load Burst Address (LBA#) low for
one clock period, which loads the starting address into
the device. The first burst data is available after the
initial access time (tIACC) from the rising edge of the
CLK that loads the burst address. After the initial
access, subsequent burst data is available tBACC after
each rising edge of CLK.
The device increments the address at each rising edge
of the clock cycles while BAA# is asserted low. The 5-
bit burst address counter is set to 00000b at the
starting address. When the burst address counter is
reaches 11111b, the device outputs the last word in the
burst sequence, and outputs a low on IND#. If the
system continues to assert BAA#, on the next CLK the
device will output the data for the starting address—the
burst address counter will have “wrapped around” to
00000b. For example, if the initial address is xxxx0h,
the data order will be 0-1-2-3.....28-29-30-31-0-1...; if
the initial address is xxxx2h, the data order will be 2-3-
4-5.....28-29-30-31-0-1-2-3...; if the initial address is
xxxx8h, the data order will be 8-9-10-11.....30-31-0-1-
2-3-4-5-6-7-8-9....; and so on. Data will be repeated if
more than 32 clocks are supplied, and BAA# remains
asserted low.
A burst mode read operation is terminated using one of
three methods:
— In the first method, CE# is asserted high. The
device in this case remains in burst mode;
asserting LBA# low terminates the previous
burst read cycle and starts a new burst read
cycle with the address that is currently valid.
— In the second method, the Burst Disable
command sequence is written to the device. The
device halts the burst operation and returns to
the asynchronous mode.
— In the third method, RESET# is asserted low. All
opertations are immediately terminated, and the
device will revert to the asynchronous mode.
Note that writing the reset command will not terminate
the burst mode.
Burst Suspend/Burst Resume Operations
The device offers Burst Suspend and Burst Resume
operations. When both OE# and BAA# are taken high,
the device removes (“suspends”) the data from the
outputs (because OE# is high), but “holds” the data
internally. The device resumes burst operation when
either OE# and/or BAA# is asserted low. Asserting the
OE# only causes the device to present the same data
that was held during the Burst Suspend operation. As
long as BAA# is high, the device will continue to output
that word of data. Asserting both OE# and BAA# low
resumes the burst operation, and on the next rising
edge of CLK, increments the counter and outputs the
next word of data.
November 3, 2006 22371C7
Am29BL802C
9
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AM29BL802C.PDF ] | |
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