PDF A6402 Data sheet ( Hoja de datos )

Número de pieza	A6402
Descripción	Universal Asynchronous Receiver/Transmitter
Fabricantes	Altera Corporation
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No Preview Available ! www.DataSheet4U.com September 1996, ver. 1 ® a6402 Universal Asynchronous Receiver/Transmitter Data Sheet Features General Description s a6402 MegaCore function implementing a universal asynchronous receiver/transmitter (UART) s Optimized for FLEX® and MAX® architectures s Uses approximately 162 FLEX logic elements (LEs) s Programmable word length, stop bits, and parity s Full duplex operation s Includes status flags for parity, framing, and overrun errors s Functionally based on the Harris HD-6402 device, except as noted in the “Variations & Clarifications” section on page 63 The a6402 MegaCore function implements a universal asynchronous receiver/transmitter (UART), which provides an interface between a microprocessor and a serial communications channel. See Figure 1. Figure 1. a6402 Symbol A6402 cls1 cls2 crl ndrr epe mr pi rrc rri sbs ntbrl tbr[7..0] trc dr fe oe pe rbr[7..0] tbre tre tro Altera Corporation A-DS-A6402-01 57 1 page Altera Corporation a6402 Universal Asynchronous Receiver/Transmitter Data Sheet Master Reset When the mr input is asserted, the pe, fe, oe, and dr outputs are asynchronously cleared and tbre and tre are asserted. The assertion of mr also sets all state machines to a default idle state. This condition does not affect the receiver buffer register. The mr input must be pulsed high at least once after power-up. When mr is deasserted, normal operation resumes at the next rising edge of trc or rrc. 1 Once the pe, fe, and oe outputs are set, the only exit condition available is through asserting mr. Control Register The control register contains the configuration of the data word, including the number of bits, calculated parity, and the number of stop bits. The crl input, an active high register enable, controls how the data word is loaded into the control register. When crl is asserted, the cls2, cls1, pi, epe, and sbs inputs are loaded on the next rising edge of the trc input. Transmitter The transmitter consists of the following elements: s Transmitter control—The transmitter control contains three interconnected state machines. The first state machine regulates the baud rate by performing a divide-by-16 operation on the trc input. The second state machine detects the low-to-high transition on ntbrl, starts the serial transmission through tro, transfers data from the transmitter buffer register to the transmitter register, and generates the status signals tbre and tre. The third state machine controls the multiplexing of data bits to the tro output. s Transmitter buffer register—The transmitter buffer register is loaded via ntbrl, an active-low register enable, that causes tbr[7..0] to be loaded from the microprocessor on the next trc clock edge. s Transmitter register—The transmitter register loads the data from the transmitter buffer register and holds that data until transmission is complete. 61 5 Page

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