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PDF PDU108H Data sheet ( Hoja de datos )
| Número de pieza | PDU108H | |
| Descripción | ECL-INTERFACED PROGRAMMABLE DELAY LINE | |
| Fabricantes | Data Delay Devices | |
| Logotipo |  |
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3-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU108H)
PDU108H
data
delay
3
®
devices, inc.
FEATURES
PACKAGES
• Digitally programmable in 8 delay steps
• Monotonic delay-versus-address variation
• Precise and stable delays
• Input & outputs fully 10KH-ECL interfaced & buffered
• Fits standard 16-pin DIP socket
GND 1 16 GND
ENB 2 15 OUT
IN 6
A0 7 10 A1
VEE 8 9 A2
GND
ENB
N/C
N/C
N/C
IN
A0
VEE
1
2
3
4
5
6
7
8
16 GND
15 OUT
14 N/C
13 N/C
12 N/C
11 N/C
10 A1
9 A2
PDU108H-xx DIP
PDU108H-xxC3 SMD
PDU108H-xxM Military DIP PDU108H-xxMC3 Mil SMD
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The PDU108H-series device is a 3-bit digitally programmable delay line.
IN Signal Input
The delay, TDA, from the input pin (IN) to the output pin (OUT) depends on
OUT Signal Output
the address code (A2-A0) according to the following formula:
A2 Address Bit 2
A1 Address Bit 1
TDA = TD0 + TINC * A
A0 Address Bit 0
ENB Output Enable
where A is the address code, TINC is the incremental delay of the device,
VEE -5 Volts
and TD0 is the inherent delay of the device. The incremental delay is
GND Ground
specified by the dash number of the device and can range from 0.5ns
through 50ns, inclusively. The enable pin (ENB) is held LOW during
normal operation. When this signal is brought HIGH, OUT is forced into a LOW state. The address is not
latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
• Total programmed delay tolerance: 5% or 1ns,
whichever is greater
• Inherent delay (TD0): 2.8ns typical
• Setup time and propagation delay:
Address to input setup (TAIS): 3.6ns
Disable to output delay (TDISO): 1.7ns typical
• Operating temperature: 0° to 70° C
• Temperature coefficient: 100PPM/°C (excludes TD0)
• Supply voltage VEE: -5VDC ± 5%
• Power Dissipation: 290mw typical (no load)
• Minimum pulse width: 25% of total delay
DASH NUMBER SPECIFICATIONS
Part
Number
PDU108H-.5
PDU108H-1
PDU108H-2
PDU108H-3
PDU108H-5
PDU108H-10
PDU108H-20
PDU108H-40
PDU108H-50
Incremental Delay
Per Step (ns)
0.5 ± 0.3
1.0 ± 0.4
2.0 ± 0.4
3.0 ± 0.5
5.0 ± 0.6
10.0 ± 1.0
20.0 ± 1.5
40.0 ± 2.0
50.0 ± 2.5
Total
Delay (ns)
3.5 ± 1.0
7.0 ± 1.0
14 ± 1.0
21 ± 1.0
35 ± 1.7
70 ± 3.5
140 ± 7.0
280 ± 14.0
350 ± 17.5
NOTE: Any dash number between .5 and 50
not shown is also available.
©2001 Data Delay Devices
Doc #97043
10/1/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
1 page  
PDU108H
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): -5.0V ± 0.1V
Input Pulse:
Standard 10KH ECL
levels
Source Impedance: 50Ω Max.
Rise/Fall Time:
2.0 ns Max. (measured
between 20% and 80%)
Pulse Width:
PWIN = 1.5 x Total Delay
Period:
PERIN = 10 x Total Delay
OUTPUT:
Load:
Cload:
Threshold:
50Ω to -2V
5pf ± 10%
(VOH + VOL) / 2
(Rising & Falling)
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PULSE
GENERATOR
OUT
TRIG
IN DEVICE UNDER OUT
TEST (DUT)
REF
IN
TRIG
OSCILLOSCOPE
ADDRESS SELECT
Test Setup
INPUT
SIGNAL
OUTPUT
SIGNAL
TRISE
PWIN
PERIN
TFALL
80% VIH 80%
50%
50%
20%
20%
VIL
DRISE
DFALL
50%
VOH
50%
Timing Diagram For Testing
VOL
Doc #97043
10/1/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet PDU108H.PDF ] | |
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