|
|
PDF PDM41024 Data sheet ( Hoja de datos )
| Número de pieza | PDM41024 | |
| Descripción | 1 Megabit Static RAM 128K x 8-Bit | |
| Fabricantes | Paradigm | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de PDM41024 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
Features
n High-speed access times
Com’l: 10, 12 and 15 ns
Ind’l: 12 and 15 ns
n Low power operation (typical)
- PDM41024SA
Active: 450 mW
Standby: 50 mW
- PDM41024LA
Active: 400 mW
Standby: 25mW
n Single +5V (±10%) power supply
n TTL-compatible inputs and outputs
n Packages
Plastic SOJ (300 mil) - TSO
Plastic SOJ (400 mil) - SO
Plastic TSOP (I)- T
PDM41024
Description
1 Megabit Static RAM
128K x 8-Bit
1
The PDM41024 is a high-performance CMOS static
RAM organized as 131,072 x 8 bits. Writing is
accomplished when the write enable (WE) and the
chip enable (CE1) inputs are both LOW and CE2 is
HIGH. Reading is accomplished when WE and CE2
remain HIGH and CE1 and OE are both LOW.
The PDM41024 operates from a single +5V power
supply and all the inputs and outputs are fully TTL-
compatible. The PDM41024 comes in two versions:
the standard power version (SA) and the low power
version (LA). The two versions are functionally the
same and differ only in their power consumption.
The PDM41024 is available in a 32-pin plastic TSOP
(I), and a 300-mil and 400-mil plastic SOJ.
2
3
4
5
6
Functional Block Diagram
Addresses
I/O 0
•
•
I/O 7
A0
•
•
•
•
•
A16
CE1
CE2
WE
OE
Control
Decoder
Input
Data
Control
• Memory
•
•
•
Matrix
•
•
•••••
Column I/O
•
•
•
7
8
9
10
11
12
Rev. 3.3 - 4/09/98
1
1 page  
PDM41024
Read Cycle No. 1(4, 5)
ADDR
DOUT
Read Cycle No. 2(2, 4, 6)
ADDR
CE1
CE2
OE
DOUT
tRC
tAA
tOH
PREVIOUS DATA VALID
tAA
tACE
tRC
tLZCE
tLZOE
tAOE
DATA VALID
tHZCE
tHZOE
DATA VALID
AC Electrical Characteristics
Description
-10(7)
-12(7)
-15
READ Cycle
Sym Min. Max. Min. Max. Min. Max. Units
READ cycle time
tRC 10 12 15
Address access time
tAA 10 12 15
Chip enable access time
tACE
10 12 15
Output hold from address change
tOH 3
3
3
Chip enable to output in low Z(1,3)
tLZCE
5
5
5
Chip disable to output in high Z(1,2,3)
tHZCE
6
6
7
Chip enable to power up time(3)
tPU 0
0
0
Chip disable to power down time(3)
tPD
10 12 15
Output enable access time
tAOE 6 6 6
Output enable to output in low Z (1,3)
tLZOE
0
0
0
Output disable to output in high Z(1,3) tHZOE 6 6 6
SHADED AREA = PRELIMINARY DATA
Notes referenced are after Data Retention Table.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 3.3 - 4/09/98
1
2
3
4
5
6
7
8
9
10
11
12
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet PDM41024.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PDM41024 | 1 Megabit Static RAM 128K x 8-Bit | Paradigm |
| PDM41028 | 1 Megabit Static RAM 256K x 4-Bit | Paradigm |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |