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ADV7392 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV7392
Beschreibung (ADV7390 - ADV7393) Low Power 10-Bit SD/HD Video Encoder
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADV7392 Datasheet, Funktion
Data Sheet
Low Power, Chip Scale,
10-Bit SD/HD Video Encoder
ADV7390/ADV7391/ADV7392/ADV7393
FEATURES
3 high quality, 10-bit video DACs
16× (216 MHz) DAC oversampling for SD
8× (216 MHz) DAC oversampling for ED
4× (297 MHz) DAC oversampling for HD
37 mA maximum DAC output current
Multiformat video input support
4:2:2 YCrCb (SD, ED, and HD)
4:4:4 RGB (SD)
Multiformat video output support
Composite (CVBS) and S-Video (Y-C)
Component YPrPb (SD, ED, and HD)
Component RGB (SD, ED, and HD)
Lead frame chip scale package (LFCSP) options
32-lead, 5 mm × 5 mm LFCSP
40-lead, 6 mm × 6 mm LFCSP
Wafer level chip scale package (WLCSP) option
30-ball, 5 × 6 WLCSP with single DAC output
Advanced power management
Patented content-dependent low power DAC operation
Automatic cable detection and DAC power-down
Individual DAC on/off control
Sleep mode with minimal power consumption
74.25 MHz 8-/10-/16-bit high definition input support
Compliant with SMPTE 274M (1080i), 296M (720p),
and 240M (1035i)
EIA/CEA-861B compliance support
NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support
NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz)
Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant
Copy generation management system (CGMS)
Closed captioning and wide screen signaling (WSS)
Integrated subcarrier locking to external video source
Complete on-chip video timing generator
On-chip test pattern generation
Programmable features
Luma and chroma filter responses
Vertical blanking interval (VBI)
Subcarrier frequency (fSC) and phase
Luma delay
High definition (HD) programmable features
(720p/1080i/1035i)
4× oversampling (297 MHz)
Internal test pattern generator
Color and black bar, hatch, flat field/frame
Fully programmable YCrCb to RGB matrix
Gamma correction
Programmable adaptive filter control
Programmable sharpness filter control
CGMS (720p/1080i) and CGMS Type B (720p/1080i)
Dual data rate (DDR) input support
Enhanced definition (ED) programmable features
(525p/625p)
8× oversampling (216 MHz output)
Internal test pattern generator
Black bar, hatch, flat field/frame
Individual Y and PrPb output delay
Gamma correction
Programmable adaptive filter control
Fully programmable YCrCb to RGB matrix
Undershoot limiter
Macrovision Rev 1.2 (525p/625p) (ADV7390/ADV7392 only)
CGMS (525p/625p) and CGMS Type B (525p)
Dual data rate (DDR) input support
Standard definition (SD) programmable features
16× oversampling (216 MHz)
Internal test pattern generator
Color and black bar
Controlled edge rates for start and end of active video
Individual Y and PrPb output delay
Undershoot limiter
Gamma correction
Digital noise reduction (DNR)
Multiple chroma and luma filters
Luma-SSAF filter with programmable gain/attenuation
PrPb SSAF
Separate pedestal control on component and
composite/S-Video output
VCR FF/RW sync mode
Macrovision Rev 7.1.L1 (ADV7390/ADV7392 only)
Copy generation management system (CGMS)
Wide screen signaling (WSS)
Closed captioning
Serial MPU interface with I2C compatibility
2.7 V or 3.3 V analog operation
1.8 V digital operation
1.8 V or 3.3 V I/O operation
Temperature range: −40°C to +85°C
W Grade automotive range: −40°C to +105°C
Qualified for automotive applications
Rev. I
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2015 Analog Devices, Inc. All rights reserved.
Technical Support
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ADV7392 Datasheet, Funktion
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
GND_IO
VDD_IO
8-BIT SD
OR
8-BIT ED/HD
DGND (2)
FUNCTIONAL BLOCK DIAGRAMS
VDD (2)
SCL SDA ALSB
SFL
AGND VAA
VBI DATA SERVICE
INSERTION
SDR/DDR
SD/ED/HD INPUT
4:2:2 TO 4:4:4
DEINTERLEAVE
ASYNC
BYPASS
YCrCb
HDTV
TEST
PATTERN
GENERATOR
MPU PORT
SUBCARRIER FREQUENCY
LOCK (SFL)
ADV7390/ADV7391
11-BIT
DAC 1
ADD
SYNC
PROGRAMMABLE
LUMINANCE
FILTER
YCrCb
TO
RGB
16×
FILTER
11-BIT
DAC 2
ADD
BURST
PROGRAMMABLE
CHROMINANCE
FILTER
SIN/COS DDS
BLOCK
16×
FILTER
11-BIT
DAC 3
PROGRAMMABLE
ED/HD FILTERS
SHARPNESS AND
ADAPTIVE FILTER
CONTROL
YCbCr
TO
RGB MATRIX
FILTER
POWER
MANAGEMENT
CONTROL
VIDEO TIMING GENERATOR
16×/4× OVERSAMPLING PLL
REFERENCE
AND CABLE
DETECT
DAC 1
DAC 2
DAC 3
RSET
RESET
HSYNC
VSYNC
CLKIN PVDD PGND EXT_LF
Figure 1. ADV7390/ADV7391 (32-Lead LFCSP)
COMP
GND_IO
VDD_IO
8-BIT SD
DGND (2)
VDD (2)
SCL SDA ALSB
SFL
AGND VAA
VBI DATA SERVICE
INSERTION
SDR/DDR
SD INPUT
4:2:2 TO 4:4:4
DEINTERLEAVE
MPU PORT
SUBCARRIER FREQUENCY
LOCK (SFL)
ADV7390BCBZ
ADD
SYNC
PROGRAMMABLE
LUMINANCE
FILTER
16×
FILTER
11-BIT
DAC 1
ADD
BURST
PROGRAMMABLE
CHROMINANCE
FILTER
SIN/COS DDS
BLOCK
16×
FILTER
DAC 1
POWER
MANAGEMENT
CONTROL
VIDEO TIMING GENERATOR
16× OVERSAMPLING PLL
REFERENCE
AND CABLE
DETECT
RSET
RESET
HSYNC
VSYNC
CLKIN PVDD PGND EXT_LF
Figure 2. ADV7390BCBZ-A (30-Ball WLCSP)
COMP
GND_IO
VDD_IO
8-/10-/16-BIT SD
OR
8-/10-/16-BIT ED/HD
DGND (2)
VDD (2)
VBI DATA SERVICE
INSERTION
SDR/DDR
SD/ED/HD INPUT
4:2:2 TO 4:4:4
DEINTERLEAVE
RGB
TO
YCrCb
MATRIX
ASYNC
BYPASS
YCrCb
HDTV
TEST
PATTERN
GENERATOR
SCL SDA ALSB
SFL
AGND VAA
MPU PORT
SUBCARRIER FREQUENCY
LOCK (SFL)
ADV7392/ADV7393
12-BIT
DAC 1
ADD
SYNC
PROGRAMMABLE
LUMINANCE
FILTER
YCrCb
TO
RGB
16×
FILTER
12-BIT
DAC 2
ADD
BURST
PROGRAMMABLE
CHROMINANCE
FILTER
SIN/COS DDS
BLOCK
16×
FILTER
12-BIT
DAC 3
PROGRAMMABLE
ED/HD FILTERS
SHARPNESS AND
ADAPTIVE FILTER
CONTROL
YCbCr
TO
RGB MATRIX
FILTER
POWER
MANAGEMENT
CONTROL
VIDEO TIMING GENERATOR
16x/4x OVERSAMPLING PLL
REFERENCE
AND CABLE
DETECT
DAC 1
DAC 2
DAC 3
RSET
RESET
HSYNC
VSYNC
CLKIN PVDD PGND EXT_LF
Figure 3. ADV7392/ADV7393 (40-Lead LFCSP)
COMP
Rev. I | Page 6 of 107

6 Page









ADV7392 pdf, datenblatt
ADV7390/ADV7391/ADV7392/ADV7393
TIMING DIAGRAMS
The following abbreviations are used in Figure 4 to Figure 11:
t9 = clock high time
t10 = clock low time
t11 = data setup time
t12 = data hold time
CLKIN
CONTROL HSYNC
INPUTS VSYNC
t9 t10
t12
Data Sheet
t13 = control output access time
t14 = control output hold time
In addition, see Table 35 for the ADV7390/ADV7391 pixel port
input configuration and Table 36 for the ADV7392/ADV7393
pixel port input configuration.
IN SLAVE MODE
PIXEL PORT
Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2
CONTROL
OUTPUTS
t11
t13
t14
Figure 4. SD Input, 8-/10-Bit 4:2:2 YCrCb, Input Mode 000
IN MASTER/SLAVE MODE
CLKIN
CONTROL
INPUTS
HSYNC
VSYNC
PIXEL PORT
PIXEL PORT
CONTROL
OUTPUTS
t9 t10
t12
Y0
Cb0
t11
Y1
Cr0
Y2
Cb2
t13
Y3
Cr2
t14
Figure 5. SD Input, 16-Bit 4:2:2 YCrCb, Input Mode 000
IN SLAVE MODE
IN MASTER/SLAVE MODE
Rev. I | Page 12 of 107

12 Page





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