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W536060A Schematic ( PDF Datasheet ) - Winbond

Teilenummer W536060A
Beschreibung (W536xx0A) VOICE/ MELODY / LCD CONTROLLER
Hersteller Winbond
Logo Winbond Logo 




Gesamt 12 Seiten
W536060A Datasheet, Funktion
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GENERAL DESCRIPTION
The W536XXXA, a member of ViewTalkTM family, is a high-performance 4-bit micro-controller (uC) with
built-in speech unit, melody unit and 64seg * 16 com LCD driver unit which includes internal regulator
,pump circuit and dedicated two pages LCD RAM. The 4-bit uC core contains dual clock source, 4-bit
ALU, two 8-bit timers, one 14 bits divider, maximum 24 pads for input or output, 8 interrupt sources and
8-level nesting for subroutine/interrupt applications. Speech unit, integrated as a single chip with
maximum 128 seconds (based on 6.4K sample rate with 5 bits MDPCM) , is capable of expanding to
512 seconds speech addressed by external memory W55XXX with serial bus interface. It can be
implemented with Winbond Power Speech using MDPCM algorithm. Melody unit provides dual tone
output and can store up to 1k notes. Power reduction mode is also built in to minimize power dissipation.
It is ideal for games, educational toys, remote controllers, watches, clocks and other application
products which incorporate both LCD display and speech.
Body
W536030A W536060A W536090A
W536120A
Voice
30 sec
60 sec
90 sec
120 sec
I/O pad
4I/O,8I
8I/O, 8I
8I/O, 8I , 8O
8I/O, 8I, 8O
(RA/RC/RD)
(RA/RB/RC/RD) (RA/RB/RC/RD/RE/RF) (RA/RB/RC/RD/RE/RF
)
WDT
disable/Enable
Y
Y
Y
Y
(Mask Option)
Sub-clock
RC/XTAL mode
Y
Y
Y
Y
(Mask Option)
RD port shared as
serial bus
Y(1) Y(1)
N
N (2)
(Mask Option)
Tri-state serial bus
(Mask Option) ( 3)
Y
Y
N
N
Cascaded Voice
ROM through Y(1) Y(1)
N
Y
serial bus (2)
(1) Share 3 pads of RD port (RD1/RDP, RD2/SPDATA and RD3/WRP)
(2) Dedicate serial bus 3 pads (RDP, SPDATA and WRP) to interface with W55XXX. Cascaded
Voice ROM can help to expand voice up to 512 sec by W55XXX chip.
(3) Tri-state serial bus mask option can float serial bus while voice playing is no active. Let this
mask option is disabled to get minimum power consumption in general.
FEATURES
Operating voltage: 2.4 volt ~ 5.5 volt
Watch dog disabled/enabled by mask option
Dual clock operating system
Main clock with RC/Crystal (400 KHz to 4 MHz)
Sub-clock with 32.768 KHz RC/Crystal by mask option
Publication Release Date: April 2000
- 1 - Revision A6






W536060A Datasheet, Funktion


  
COM0COM7
O
COM8 / PORTP.0
COM11/PORTP.3
COM12/PORTO.0
COM15/PORTO.3
DH1, DH2 (6)
O/O
O/I
O
V3 ~ V6 (6)
O
V2 (6)
I/O
VSSP (7)
VSS (7)
VDDP (7)
VDD (7)
I
I
I
I
LCD common signal output pads either 1/16 duty or 1/8 duty. The LCD frame rate
is controlled by LCDM1 register, and default value LCDM1=0111b with 64Hz
frame rate.
LCD common signal output pads, or shared as general output by register
LCDM3.2 when in 1/8 duty mode. Default function is common function.
LCD common signal output pads, or shared as general input by register LCDM3.2
when in 1/8 duty mode. Default function is common function and PM5.2=0 to
inhibit LCD waveform abnormal.
Connection terminal for voltage double capacitor with 0.1uF. The DH2 connects
to capacitor positive node and DH1 negative node if polar capacitor is used.
LCD COM/SEG output driving voltage. Need an external 0.1uF capacitor to every
pad terminal.
Voltage regulator output pad. An external capacitor is a must. Output level can
be controlled from 0~Fh by LCDM4 register. If internal pump is enabled
(LCDM3.3=0 and default value), LCD operating voltage (VLCD) will be 4*V2 or
5*V2 depending on 1/4 bias or 1/5 bias. A limitation should be noted that VLCD
must be higher than (VDD-0.5v) to avoid chip leakage current. While external
reference voltage is selected (LCDM3.3=1), V2 pad input voltage can not be over
1.5 Volt to inhibit chip damage.
Power ground for PWM or DAC playing output.
Power ground
Power source for PWM or DAC playing output.
Power ground.
(4) RD1~3 are shared as RDP/SPDATA/WRP to interface with W55XXX @W536030A/060A
(5) @W536120A only
(6) 0.1uF is default value, and capacitor value should be larger than 0.1uF if LCD dot size over
0.5mm * 0.5mm.
(7) External application circuit should connect together, please refer to APPLICATION CIRCUIT. To
sure chip operation properly, please bond all VDD, VDDP,VSS and VSSP pads and connect VSS
and VSSP from chip outside PCB circuit.
Publication Release Date:April 2000
- 6 - Revision A6

6 Page









W536060A pdf, datenblatt


  
APPLICATION CIRCUIT---2 : Sub clock with Crystal mode
VLCD> (VDD-0.5v)
Panel
RA0~3
RB0~3
RC0~3
RD0~3
RE0~3
RF0~3
VDD
( 2) * R5
RES
Battery
C9
VDDP
C11
C10
R4
VDD
R1 ROSC
R3 XIN
C7
C8
X32IN
32.768kHz
X32O
VDDP
W536xxxA
470
(*3)
PWMP/DAC
PWMN
DH1
DH2
+ C-1
V6 C6
(*1)
V5 C5
V4 C4
V3 C3
V2 C2
Component C1~C6 C7,C8 C9,C10 C11 R1 R2 R3
R4
Value
0.1uF 15~20pF 0.1uF 1uF 680K - 680Kohm/1Mhz 100
330Kohm/2Mhz
200Kohm/3Mhz
130Kohm/4Mhz
Note:
(1) C1~C6 depends on LCD panel dot size.
(2) Option R5 equals to 100if high noise immunity is needed.
(3) For DAC option application.
(4) To sure chip operation properly, please bond all VDDP, VDD, VSSP and VSS .
Publication Release Date:April 2000
- 12 -
Revision A6

12 Page





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