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PDF ADSP-21266 Data sheet ( Hoja de datos )
| Número de pieza | ADSP-21266 | |
| Descripción | SHARC Embedded Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Code compatibility—at assembly level, uses the same
instruction set as other SHARC DSPs
The ADSP-21266 processes high performance audio while
enabling low system costs
Audio decoders and post processor algorithms support:
Nonvolatile memory can be configured to contain a combi-
nation of PCM 96 kHz, Dolby® Digital, Dolby Digital
Surround EXTM, DTS-ESTM Discrete 6.1, DTS-ES Matrix 6.1,
DTS® 96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMA-
PRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and
DTS Neo:6TM
Various multichannel surround-sound decoders are con-
tained in ROM. For configurations of decoder algorithms,
see Table 2 on Page 6.
SHARC®
Embedded Processor
ADSP-21266
Single-instruction multiple-data (SIMD) computational archi-
tecture—two 32-bit IEEE floating-point/32-bit fixed-point/
40-bit extended precision floating-point computational
units, each with a multiplier, ALU, shifter, and register file
High bandwidth I/O—a parallel port, an SPI® port, six serial
ports, a digital audio interface (DAI), and JTAG
DAI incorporates two precision clock generators (PCGs), an
input data port (IDP) that includes a parallel data acquisi-
tion port (PDAP), and three programmable timers, all
under software control by the signal routing unit (SRU)
On-chip memory—2M bits of on-chip SRAM and a dedicated
4M bits of on-chip mask-programmable ROM
The ADSP-21266 is available with a 150 MHz or a 200 MHz
core instruction rate. For complete ordering information,
see Ordering Guide on Page 44.
CORE PROCESSOR
TIME R
INSTRUCTION
CACHE
32 ؋ 48-BIT
DAG1
DAG2
8 ؋ 4 ؋ 32 8 ؋ 4 ؋ 32
PROG RAM
SEQ UENCER
DUAL PORTED MEMORY
BLOCK 0
S RAM
1M BIT
ROM
2M BIT
ADDR
DATA
DUAL PORTED MEMORY
BLO CK 1
S RAM
1M BIT
ROM
2M BIT
ADDR
DATA
PM ADDRESS BUS
DM ADDRESS BUS
32
32
PROCES SING
ELEMENT
( PEX )
PRO CESSING
ELEMENT
( PE Y)
PX REGI STER
64 PM DATA BUS
64 DM DATA BUS
DMA CONTRO LLER
2 2 C HA N N ELS
4
SPI PORT (1)
JTAG TEST & EMULATION
6
S
SERIAL PORTS (6)
20 SIGNAL
RO UTI NG
UNI T
I NP UT
DATA PORTS (8)
PARALLEL DATA
ACQUISITION PORT
PRECISION CLOCK
GENERATORS (2)
3
TIMERS (3)
DIGITAL AUDIO INTERFACE
I/O PROCESSOR
IOD IOA
(32) (18)
GPIO FLAGS/
IRQ /TIMEXP
4
IOP
RE GISTE RS
(MEMORY MAPPED)
CO NTROL,
S TATUS ,
DATA BUFFERS
AD D R ES S/
D A TA BU S / GPIO
CON TR OL/GPIO
P ARALLEL
P ORT
16
3
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
FAX: 781.461.3113 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
ADSP-21266
CLOCK
2
2
3
A DC
(OPTI ONAL)
C LK
FS
S DAT
DAC
(OP TIONAL)
C LK
FS
S DAT
CLKI N
XT A L
CLK_ CFG 1– 0
BOOTCFG1– 0
FLAG 3– 1
ADS P-21266
CLKOUT
A LE
AD15 –0
RD
WR
FL A G0
DAI_ P1
DAI_P 2
DAI_P 3
DAI_ P1 8
DAI_ P19
DAI_P 20
SR U
SC L K 0
SFS0
SD 0A
SD 0B
S PORT0
SP ORT1
SPO RT2
S PORT3
SPO RT4
SPOR T 5
DAI
CLK
FS
PCG A
P CGB
RESE T
J TAG
6
L AT C H
ADDR
DA T A
OE
WE
CS
PARALLE L
PO RT
RAM, ROM
BOOT ROM
I/O DEVICE
Figure 2. ADSP-21266 System Sample Configuration
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each
processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2126x enhanced Har-
vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0–R15 and in PEY as S0–S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21266 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 1 on Page 1). With the ADSP-21266’s separate pro-
gram and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a
single cycle.
Instruction Cache
The ADSP-21266 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators with Zero-Overhead Hardware
Circular Buffer Support
The ADSP-21266’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program-
ming of delay lines and other data structures required in digital
signal processing, and are commonly used in digital filters and
Rev. B | Page 5 of 44 | May 2005
5 Page 
ADSP-21266
PIN FUNCTION DESCRIPTIONS
ADSP-21266 pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs iden-
tified as asynchronous (A) can be asserted asynchronously to
CLKIN (or to TCK for TRST). Tie or pull unused inputs to
VDDEXT or GND, except for the following:
• DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST, TDI
and AD15–0 (NOTE: These pins have internal pull-up
resistors.)
The following symbols appear in the Type column of Table 3:
A = asynchronous, G = ground, I = input, O = output,
P = power supply, S = synchronous, (A/D) = active drive,
(O/D) = open drain, and T = three-state.
Table 3. Pin Descriptions
Pin
AD15–0
RD
WR
ALE
FLAG3–0
Type
I/O/T
O
O
O
I/O/A
State During and
After Reset
Function
Rev. 0.1 silicon—
AD15–0 pins are
driven low both
during and after
reset.
Parallel Port Address/Data. The ADSP-21266 parallel port and its corresponding
DMA unit output addresses and data for peripherals on these multiplexed pins. The
multiplex state is determined by the ALE pin. The parallel port can operate in either
8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. See Address
Data Modes on Page 14 for details of the AD pin operation.
Rev. 0.2 silicon—
AD15–0 pins are
three-stated and
pulled high both
during and after
reset.
For 8-bit mode: ALE is automatically asserted whenever a change occurs in the
upper 16 external address bits, A23–8; ALE is used in conjunction with an external
latch to retain the values of the A23–8.
For 16-bit mode: ALE is automatically asserted whenever a change occurs in the
address bits, A15–0; ALE is used in conjunction with an external latch to retain the
values of the A15–0. To use these pins as flags (FLAG15–0) set (=1) Bit 20 of the
SYSCTL register and disable the parallel port. See Table 4 on Page 14 for a list of how
the AD15–0 pins map to the flag pins. When configured in the IDP_PDAP_CTL
register, the IDP Channel 0 can use these pins for parallel input data.
Output only, driven Parallel Port Read Enable. RD is asserted low whenever the DSP reads 8-bit or
high1
16-bit data from an external memory device. When AD15–0 are flags, this pin
remains deasserted.
Output only, driven Parallel Port Write Enable. WR is asserted low whenever the DSP writes 8-bit or
high1
16-bit data to an external memory device. When AD15–0 are flags, this pin remains
deasserted.
Output only, driven
low1
Parallel Port Address Latch Enable. ALE is asserted whenever the DSP drives a
new address on the parallel port address pin. On reset, ALE is active high. However,
it can be reconfigured using software to be active low. When AD15–0 are flags, this
pin remains deasserted.
Three-state
Flag Pins. Each FLAG pin is configured via control bits as either an input or output.
As an input, it can be tested as a condition. As an output, it can be used to signal
external peripherals. These pins can be used as an SPI interface slave select output
during SPI mastering. These pins are also multiplexed with the IRQx and the TIMEXP
signals.
In SPI master boot mode, FLAG0 is the slave select pin that must be connected to
an SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When
Bit 16 is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0.
When Bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1.
When Bit 18 is set (=1) in the SYSCTL register, FLAG2 is configured as IRQ2.
When Bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP, which
indicates that the system timer has expired.
Rev. B | Page 11 of 44 | May 2005
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADSP-21266.PDF ] | |
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