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PCF5271 Schematic ( PDF Datasheet ) - Freescale Semiconductor

Teilenummer PCF5271
Beschreibung 32-bit Embedded Controller Division
Hersteller Freescale Semiconductor
Logo Freescale Semiconductor Logo 




Gesamt 30 Seiten
PCF5271 Datasheet, Funktion
www.DataSheet4U.com
Freescale Semiconductor
Hardware Specification
MCF5271EC
Rev. 1.2, 12/2004
MCF5271 Integrated
Microprocessor
Hardware Specification
32-bit Embedded Controller Division
The MCF5271 family is a highly integrated
implementation of the ColdFire® family of reduced
instruction set computing (RISC) microprocessors. This
document describes pertinent features and functions of
the MCF5271 family. The MCF5271 family includes the
MCF5271 and MCF5270 microprocessors. The
differences between these parts are summarized below in
Table 1. This document is written from the perspective of
the MCF5271 and unless otherwise noted, the
information applies also to the MCF5270.
The MCF5271 family combines low cost with high
integration on the popular version 2 ColdFire core with
over 96 (Dhrystone 2.1) MIPS at 100MHz. Positioned
for applications requiring a cost-sensitive 32-bit
solution, the MCF5271 family features a 10/100 Ethernet
MAC and optional hardware encryption to ensure the
application can be connected and protected. In addition,
the MCF5271 family features an enhanced Multiply
Accumulate Unit (eMAC), large on-chip memory (64
Kbytes SRAM, 8 Kbytes configurable cache), and a
32-bit SDR SDRAM memory controller.
Table of Contents
1 MCF5271 Family Configurations ..................... 2
2 Block Diagram ................................................. 2
3 Features .......................................................... 4
4 Signal Descriptions........................................ 12
5 Modes of Operation....................................... 16
6 Design Recommendations ............................ 19
7 Mechanicals/Pinouts and Part Numbers ....... 27
8 Preliminary Electrical Characteristics............ 32
9 Documentation .............................................. 55
Technical Data
© Freescale Semiconductor, Inc., 2004. All rights reserved.






PCF5271 Datasheet, Funktion
Features
— 24 to 50 MHz oscillator reference frequency for 1:1 mode
— Separate clock output pin
— Interrupt Controllers (x2)
– Support for up to 41 interrupt sources organized as follows: 34 fully-programmable
interrupt sources and 7 fixed-level external interrupt sources
— Unique vector number for each interrupt source
— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
— Support for hardware and software interrupt acknowledge (IACK) cycles
— Combinatorial path to provide wake-up from low power modes
• DMA Controller
— Four fully programmable channels
— Dual-address and single-address transfer support with 8-, 16- and 32-bit data capability along
with support for 16-byte (4 x 32-bit) burst transfers
— Source/destination address pointers that can increment or remain constant
— 24-bit byte transfer counter per channel
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle steal support
— Software-programmable connections between the 12 DMA requesters in the UARTs (3),
32-bit timers (4), plus external logic (4), and the four DMA channels (4)
• External Bus Interface
— Glueless connections to external memory devices (e.g., SRAM, Flash, ROM, etc.)
— SDRAM controller supports 8-, 16-, and 32-bit wide memory devices
— Support for n-1-1-1 burst fetches from page mode Flash
— Glueless interface to SRAM devices with or without byte strobe inputs
— Programmable wait state generator
— 32-bit bidirectional data bus
— 24-bit address bus
— Up to eight chip selects available
— Byte/write enables (byte strobes)
— Ability to boot from external memories that are 8, 16, or 32 bits wide
• Chip Configuration Module (CCM)
— System configuration during reset
— Selects one of four clock modes
— Sets boot device and its data port width
— Configures output pad drive strength
— Unique part identification number and part revision number
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2
6 Freescale Semiconductor

6 Page









PCF5271 pdf, datenblatt
Signal Descriptions
3.20 GPIO
Unused bus interface and peripheral pins on the MCF5271 can be used as discrete general-purpose inputs
and outputs. These are managed by a dedicated GPIO module that logically groups all pins into ports
located within a contiguous block of memory-mapped control registers.
All of the pins associated with the external bus interface may be used for several different functions. Their
primary function is to provide an external memory interface to access off-chip resources. When not used
for this, all of the pins may be used as general-purpose digital I/O pins. In some cases, the pin function is
set by the operating mode, and the alternate pin functions are not supported.
The digital I/O pins on the MCF5271 are grouped into 8-bit ports. Some ports do not use all eight bits.
Each port has registers that configure, monitor, and control the port pins.
4 Signal Descriptions
This section describes signals that connect off chip, including a table of signal properties. For a more
detailed discussion of the MCF5271 signals, consult the MCF5235 Reference Manual (MCF5235RM).
4.1 Signal Properties
Table 2 lists all of the signals grouped by function. The “Dir” column is the direction for the primary
function of the pin. Refer to Section 7, “Mechanicals/Pinouts and Part Numbers,” for package diagrams.
NOTE
In this table and throughout this document a single signal within a group is
designated without square brackets (i.e., A24), while designations for
multiple signals within a group use brackets (i.e., A[23:21]) and is meant to
include all signals within the two bracketed numbers when these numbers
are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality.
Pins that are muxed with GPIO will default to their GPIO functionality.
Table 2. MCF5270 and MCF5271 Signal Information and Muxing
Signal Name
GPIO
Alternate 1 Alternate 2 Dir.1
MCF5270
MCF5271
160 QFP
MCF5270
MCF5271
196 MAPBGA
RESET
RSTOUT
Reset
— —I
— —O
83
82
N13
P13
EXTAL
XTAL
Clock
— —I
— —O
86
85
M14
N14
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2
12 Freescale Semiconductor

12 Page





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