PDF CY7C1440AV33 Data sheet ( Hoja de datos )

Número de pieza	CY7C1440AV33
Descripción	(CY7C144xAV33) Sync SRAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com PRELIMINARY CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Features Functional Description[1] • Supports bus operation up to 250 MHz • Available speed grades are 250, 200,167 MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 3.2 ns (for 200-MHz device) — 3.4 ns (for 167-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Single Cycle Chip Deselect • Offered in JEDEC-standard 100-pin TQFP, 165-Ball fBGA and 209-Ball fBGA packages • Also available in lead-free packages • IEEE 1149.1 JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode Option The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1,048,576 x 36, 2,097,152 x 18 and 524,288 x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining CChEi3p[2E])n, aBbulrest(CCEo1n)t,rodleipntphu-etsxp(AaDnsSioCn, Chip Enables (CE2 and ADSP, and ADV), Write Enables (BWX and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide 250 MHz 200 MHz 167 MHz Maximum Access Time 2.6 3.2 3.4 Maximum Operating Current 475 425 375 Maximum CMOS Standby Current 100 100 100 Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Notes: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. 2. CE3, CE2 are for TQFP and 165 fBGA package only. Unit ns mA mA Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-05383 Rev. B Revised January 31, 2005 1 page Pin Configurations (continued) 123 A NC / 288M B NC A A CE1 CE2 C DQPC NC VDDQ D DQC DQC VDDQ E DQC DQC VDDQ F DQC DQC VDDQ G DQC DQC VDDQ H NC NC NC J DQD DQD VDDQ K DQD DQD VDDQ L DQD DQD VDDQ M DQD DQD VDDQ N DQPD NC VDDQ P NC NC / 72M A R MODE A A 123 A NC / 288M B NC A A CE1 CE2 C NC NC VDDQ D NC DQB VDDQ E NC DQB VDDQ F NC DQB VDDQ G NC DQB VDDQ H NC NC NC J DQB NC VDDQ K DQB NC VDDQ L DQB NC VDDQ M DQB NC VDDQ N DQPB NC VDDQ P NC NC / 72M A R MODE A A PRELIMINARY CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 165-ball fBGA CY7C1440AV33 (1 Mbit x 36) 4 567 BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO A TMS A0 TCK CY7C1442AV33 (2 Mbit x 18) 4 BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 11 A NC A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A NC / 144M DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA A AA 10 11 AA A NC / 144M NC DQPA NC DQA NC DQA NC DQA NC DQA NC ZZ DQA NC DQA NC DQA NC DQA NC NC NC AA AA Document #: 38-05383 Rev. B Page 5 of 27 5 Page PRELIMINARY CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Truth Table for Read/Write[5, 9, 10] Function ( CY7C1446AV33) Read Read Write Byte x – (DQx and DQPx) Write All Bytes Write All Bytes IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 incor- porates a serial boundary scan test access port (TAP). This part is fully compliant with IEEE Standard 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are inter- nally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. TAP Controller State Diagram 1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 1 0 1 CAPTURE-DR 0 SHIFT-DR 0 1 EXIT1-DR 1 0 PAUSE-DR 0 1 0 EXIT2-DR 1 UPDATE-DR 10 SELECT IR-SCAN 1 0 1 CAPTURE-IR 0 SHIFT-IR 0 1 EXIT1-IR 1 0 PAUSE-IR 0 1 0 EXIT2-IR 1 UPDATE-IR 10 GW BWE BWx HHX H L All BW = H HL L H L All BW = L LXX Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most signif- icant bit (MSB) of any register. (See Tap Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.) The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Document #: 38-05383 Rev. *B Page 11 of 27 11 Page

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