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PDF WEDPNF8M722V-XBX Data sheet ( Hoja de datos )
| Número de pieza | WEDPNF8M722V-XBX | |
| Descripción | 8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package | |
| Fabricantes | White Electronic Designs | |
| Logotipo |  |
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White Electronic Designs
WEDPNF8M722V-XBX
8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module
Multi-Chip Package ADVANCED*
FEATURES
n Sector Architecture
n Package:
• 275 Plastic Ball Grid Array (PBGA), 32mm x 25mm
n Commercial, Industrial and Military Temperature Ranges
n Weight:
• WEDPNF8M722V-XBX - 2.5 grams typical
•One 16KByte, two 8KBytes, one 32KByte, and fifteen
64KBytes in byte mode
•One 8K word, two 4K words, one 16K word, and
fifteen 32K word sectors in word mode.
•Any combination of sectors can be concurrently
erased. Also supports full chip erase
SDRAM PERFORMANCE FEATURES
n Organized as 8M x 72
n High Frequency = 100, 125MHz
n Single 3.3V ±0.3V power supply
n Fully Synchronous; all signals registered on positive
edge of system clock cycle
n Internal pipelined operation; column address can be
changed every clock cycle
n Internal banks for hiding row access/precharge
n Programmable Burst length 1,2,4,8 or full page
n 4096 refresh cycles
FLASH PERFORMANCE FEATURES
n Boot Code Sector Architecture (Bottom)
n Embedded Erase and Program Algorithms
n Erase Suspend/Resume
•Supports reading data from or programing data to a
sector not being erased
BENEFITS
n 44% SPACE SAVINGS
n Reduced part count
n Reduced I/O count
•25% I/O Reduction
n Suitable for hi-reliability applications
n SDRAM Upgradeable to 16M x 72 density (contact
n User Configurable as 2Mx8, 1M x16 or 512K x 32
factory for information)
n Access Times of 100, 120, 150ns
n 3.3 Volt for Read and Write Operations
* This data sheet describes a product that may or may not be under
development and is subject to change or cancellation without notice.
n 1,000,000 Erase/Program Cycles
September 2002 Rev. 2
1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
1 page  
White Electronic Designs WEDPNF8M722V-XBX
Signal Name
CAS3
DQML3
DQMH3
CS4
WE4
CLK4
CKE4
RAS4
CAS4
DQML4
DQMH4
DQ0 - 15
DQ16 - 31
DQ32 - 47
DQ48 - 63
DQ64 - 79
DNU
PACKAGE PINOUT LISTING (CONTINUED)
Pin Number
R3
U2
N3
T10
U9
R9
R10
U10
V10
V9
T9
E1, F1, E2, G1, F2, H1, J1, G2, A3, A2, B2, C2, B1, D2, C1, D1,
E16, F16, G16, H16, E17, F17, G17, H17, D18, A17, B17, C17, D17, A16, B16, C16
R17, T17, U16, V16, T16, R16, U17, P18, N16, P16, P17, M16, M17, N17, N18, L17
R1, P2, T1, R2, P3, U1, V2, T2, M2, N2, L2, M1, P1, N1, L1, K1
U8, U6, V5, V6, U7, U5, V7, V8, R8, R6, T8, T6, R7, R5, T7, T5
F6, G5, R14, U14, V1
5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
5 Page 
White Electronic Designs WEDPNF8M722V-XBX
TABLE 3 TRUTH TABLE - COMMANDS AND DQM OPERATION (NOTE 1)
NAME (FUNCTION)
CS RAS CAS WE DQM
ADDR
I/Os
COMMAND INHIBIT (NOP)
H XXXX
X
X
NO OPERATION (NOP)
L HHHX
X
X
ACTIVE (Select bank and activate row) ( 3)
L L H H X Bank/Row
X
READ (Select bank and column, and start READ burst) (4)
L H L H L/H 8 Bank/Col
X
WRITE (Select bank and column, and start WRITE burst) (4)
L H L L L/H 8 Bank/Col Valid
BURST TERMINATE
L H H L X X Active
PRECHARGE (Deactivate row in bank or banks) ( 5)
L LHLX
Code
X
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
L L LHX
X
X
LOAD MODE REGISTER (2)
L L L L X Op-Code
X
Write Enable/Output Enable (8)
– – – – L – Active
Write Inhibit/Output High-Z (8)
– – – – H – High-Z
NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-11 define the op-code written to the Mode Register.
3. A0-11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1
determine which bank is being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs (two-clock delay).
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands
from being executed by the SDRAM, regardless of whether
the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.
BA0, BA1 inputs selects the bank, and the address pro-
vided on inputs A0-11 selects the row. This row remains
active (or open) for accesses until a PRECHARGE command
is issued to that bank. A PRECHARGE command must be
issued before opening a different row in the same bank.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a
NOP to an SDRAM which is selected (CS is LOW). This pre-
vents unwanted commands from being registered during
idle or wait states. Operations already in progress are not
affected.
LOAD MODE REGISTER
The Mode Register is loaded via inputs A0-11. See Mode
Register heading in the Register Definition section. The LOAD
MODE REGISTER command can only be issued when all
banks are idle, and a subsequent executable command
cannot be issued until tMRD is met.
READ
The READ command is used to initiate a burst read access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-8 se-
lects the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed will
be precharged at the end of the READ burst; if AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses. Read data appears on the I/Os sub-
ject to the logic level on the DQM inputs two clocks earlier.
If a given DQM signal was registered HIGH, the correspond-
ing I/Os will be High-Z two clocks later; if the DQM signal
was registered LOW, the I/Os will provide valid data.
ACTIVE
The ACTIVE command is used to open (or activate) a row in
a particular bank for a subsequent access. The value on the
WRITE
The WRITE command is used to initiate a burst write access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-8 selects
1 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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