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PDF ADS1230 Data sheet ( Hoja de datos )
| Número de pieza | ADS1230 | |
| Descripción | 20-Bit Analog-to-Digital Converter | |
| Fabricantes | Burr-Brown | |
| Logotipo |  |
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BurrĆBrown Products
from Texas Instruments
ADS1230
20-Bit Analog-to-Digital Converter
For Bridge Sensors
SBAS366 – OCTOBER 2006
FEATURES
• Complete Front-End for Bridge Sensor
• Onboard PGA with Gain of 64 or 128
• Onboard Oscillator
• RMS Noise:
40nV at 10SPS (G = 128)
88nV at 80SPS (G = 128)
• 18-Bit Noise-Free Resolution
• Selectable 10SPS or 80SPS Data Rates
• Simultaneous 50Hz and 60Hz Rejection at
10SPS
• External Voltage Reference up to 5V for
Ratiometric Measurements
• Simple, Pin-Driven Control
• Two-Wire Serial Digital Interface
• Tiny 16-pin TSSOP Package
• Supply Range: 2.7V to 5.3V
• –40°C to +85°C Temperature Range
APPLICATIONS
• Weigh Scales
• Strain Gauges
• Pressure Sensors
• Industrial Process Control
DESCRIPTION
The ADS1230 is a precision 20-bit analog-to-digital
converter (ADC). With an onboard low-noise
programmable gain amplifier (PGA), onboard
oscillator, and precision 20-bit delta-sigma ADC, the
ADS1230 provides a complete front-end solution for
bridge sensor applications including weigh scales,
strain gauges, and pressure sensors.
The low-noise PGA has a gain of 64 or 128,
supporting a full-scale differential input of ±39mV or
±19.5mV, respectively. The delta-sigma ADC has
20-bit effective resolution and is comprised of a
3rd-order modulator and 4th-order digital filter. Two
data rates are supported: 10SPS (with both 50Hz
and 60Hz rejection) and 80SPS. The ADS1230 can
be clocked by the internal oscillator or an external
clock source. Offset calibration is performed
on-demand, and the ADS1230 can be put in a
low-power standby mode or shut off completely in
power-down mode.
All of the features of the ADS1230 are controlled by
dedicated pins; there are no digital registers to
program. Data are output over an easily-isolated
serial interface that connects directly to the MSP430
and other microcontrollers.
The ADS1230 is available in a TSSOP-16 package
and is specified from –40°C to +85°C.
AVDD
CAP
AINP
AINN
Gain = 64 or 128
PGA
REFP REFN DVDD
DS ADC
PDWN
DRDY/DOUT
SCLK
Internal
Oscillator
SPEED
AGND GAIN
CAP
CLKIN
DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
1 page  
ADS1230
www.ti.com
PIN CONFIGURATION
PW PACKAGE
TSSOP-16
(Top View)
DVDD 1
DGND 2
CLKIN 3
GAIN 4
CAP 5
CAP 6
AINP 7
AINN 8
ADS1230
16 DRDY/DOUT
15 SCLK
14 PDWN
13 SPEED
12 AVDD
11 AGND
10 REFP
9 REFN
SBAS366 – OCTOBER 2006
NAME
DVDD
DGND
CLKIN
GAIN
CAP
CAP
AINP
AINN
REFN
REFP
AGND
AVDD
SPEED
PDWN
SCLK
DRDY/DOUT
TERMINAL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ANALOG/DIGITAL
INPUT/OUTPUT
Digital
Digital
Digital/Digital Input
Digital Input
Analog
Analog
Analog Input
Analog Input
Analog Input
Analog Input
Analog
Analog
Digital Input
Digital Input
Digital Input
Digital Output
PIN DESCRIPTIONS
DESCRIPTION
Digital Power Supply: 2.7V to 5.3V
Digital Ground
External Clock Input: typically 4.9152MHz. Tie low to activate internal oscillator.
PGA Gain Select
GAIN
PGA
0 64
1 128
Gain Amp Bypass Capacitor Connection
Gain Amp Bypass Capacitor Connection
Positive Analog Input
Negative Analog Input
Negative Reference Input
Positive Reference Input
Analog Ground
Analog Power Supply, 2.7V to 5.3V
Data Rate Select:
SPEED
DATA RATE
0 10SPS
1 80SPS
Power-Down: Holding this pin low powers down the entire converter and resets the ADC.
Serial Clock: Clock out data on the rising edge. Also used to initiate Offset Calibration and Sleep
modes. See the Offset Calibration, Standby Mode, and Standby Mode with Offset Calibration sections
for more details.
Dual-Purpose Output:
Data Ready: Indicates valid data by going low.
Data Output: Outputs data, MSB first, on the first rising edge of SCLK.
Submit Documentation Feedback
5
5 Page 
ADS1230
www.ti.com
VOLTAGE REFERENCE INPUTS
(REFP, REFN)
The voltage reference used by the modulator is
generated from the voltage difference between
REFP and REFN: VREF = REFP – REFN. The
reference inputs use a structure similar to that of the
analog inputs. In order to increase the reference
input impedance, a switching buffer circuitry is used
to reduce the input equivalent capacitance. A
simplified diagram of the circuitry on the reference
inputs is shown in Figure 19. The switches and
capacitors can be modeled with an effective
impedance of:
Z EFF
+
1
2fMODCBUF
Where:
fMOD = modulator sampling frequency (76.8kHz)
CBUF = input capacitance of the buffer
For the ADS1230:
Z EFF
+
1
(2)(76.8kHz)(32.5fF)
+
200MW
REFP
REFN
AVDD
CBUF
AVDD
ESD
Protection
ZEFF = 200MW(1)
(1) fMOD = 76.8kHz
Figure 19. Simplified Reference Input Circuitry
SBAS366 – OCTOBER 2006
ESD diodes protect the reference inputs. To prevent
these diodes from turning on, make sure the
voltages on the reference pins do not go below GND
by more than 100mV, and likewise, do not exceed
AVDD by 100mV:
GND – 100mV < (REFP or REFN) < AVDD + 100mV
CLOCK SOURCES
The ADS1230 can use an external clock source or
internal oscillator to accommodate a wide variety of
applications. Figure 20 shows the equivalent circuitry
of the clock source. The CLK_DETECT block
determines whether the crystal oscillator/external
clock signal is applied to the CLKIN pin so that the
internal oscillator is bypassed or activated. When the
CLKIN pin frequency is above ~200kHz, the
CLK_DETECT output goes low and shuts down the
internal oscillator. When the CLKIN pin frequency is
below ~200kHz, the CLK_DETECT output goes high
and activates the internal oscillator. It is highly
recommended to hard-wire the CLKIN pin to ground
when the internal oscillator is chosen.
CLKIN
CLK_DETECT
S0 S1
MUX
Internal
Oscillator
S
To ADC
EN
Figure 20. Equivalent Circuitry of the Clock
Source
An external clock may be used by driving the CLKIN
pin directly. The Electrical Characteristics table
shows the allowable frequency range. The clock
input may be driven with 5V logic, regardless of the
DVDD or AVDD voltage.
Submit Documentation Feedback
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet ADS1230.PDF ] | |
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