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AD7762 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7762
Beschreibung With On-Chip Buffer 625 KSPS
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 28 Seiten
AD7762 Datasheet, Funktion
www.DataSheet4U.com
625 kSPS, 24-Bit, 109 dB Σ−Δ ADC
With On-Chip Buffer
AD7762
FEATURES
120 dB dynamic range at 78 kHz output data rate
109 dB dynamic range at 625 kHz output data rate
112 dB SNR at 78 kHz output data rate
106 dB SNR at 625 kHz output data rate
625 kHz maximum fully filtered output word rate
Programmable over-sampling rate (32× to 256×)
Fully differential modulator input
On-chip differential amplifier for signal buffering
Low-pass finite impulse response (FIR) filter with default or
user-programmable coefficients
Overrange alert bit
Digital offset and gain correction registers
Filter bypass modes
Low power and power-down modes
Synchronization of multiple devices via SYNC pin
APPLICATIONS
Data acquisition systems
Vibration analysis
Instrumentation
GENERAL DESCRIPTION
The AD7762 is a high performance, 24-bit Σ-Δ analog-to-
digital converter (ADC). It combines wide input bandwidth
and high speed with the benefits of Σ-Δ conversion with a
performance of 106 dB SNR at 625 kSPS, making it ideal for
high speed data acquisition. Wide dynamic range combined
with significantly reduced antialiasing requirements simplify
the design process. An integrated buffer to drive the reference,
a differential amplifier for signal buffering and level shifting, an
overrange flag, internal gain and offset registers, and a low-pass
digital FIR filter make the AD7762 a compact, highly integrated
data acquisition device requiring minimal peripheral com-
ponent selection. In addition, the device offers programmable
decimation rates, and the digital FIR filter can be adjusted if
the default characteristics are not appropriate to the application.
The AD7762 is ideal for applications demanding high SNR
without a complex front end signal processing design.
The differential input is sampled at up to 40 MSPS by an analog
modulator. The modulator output is processed by a series of low-
pass filters, the final filter having default or user-programmable
FUNCTIONAL BLOCK DIAGRAM
VIN– VIN+
VREF+
BUF
DIFF
MCLK
SYNC
RESET
AD7762
CONTROL LOGIC
I/O
OFFSET AND GAIN
REGISTERS
MULTIBIT
Σ-Δ
MODULATOR
RECONSTRUCTION
PROGRAMMABLE
DECIMATION
FIR FILTER
ENGINE
AVDD1
AVDD2
AVDD3
AVDD4
DECAPA/B
RBIAS
AGND
VDRIVE
DVDD
DGND
CS RD/WR DRDY DB0 TO DB15
Figure 1.
coefficients. The sample rate, filter corner frequencies, and output
word rate are set by a combination of the external clock frequency
and the configuration registers of the AD7762.
The reference voltage supplied to the AD7762 determines the
analog input range. With a 4 V reference, the analog input range
is ±3.2 V differential biased around a common mode of 2 V.
This common-mode biasing can be achieved using the on-chip
differential amplifier, further reducing the external signal
conditioning requirements.
The AD7762 is available in an exposed paddle, 64-lead TQFP
and is specified over the industrial temperature range from
−40°C to +85°C.
Table 1. Related Devices
Part No. Description
AD7760 24-bit, 2.5 MSPS, 100 dB Σ-Δ, parallel interface
AD7763 24-bit, 625 kSPS, 109 dB Σ-Δ, serial interface
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.






AD7762 Datasheet, Funktion
AD7762
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameters
AVDD1 to GND
AVDD2–AVDD4 to GND
DVDD to GND
VDRIVE to GND
VIN+, VIN– to GND
Digital input voltage to GND1
MCLK to MCLKGND
VREF to GND2
AGND to DGND
Input Current to Any Pin
Except Supplies3
Operating Temperature Range
Commercial
Storage Temperature Range
Junction Temperature
TQFP Exposed Paddle Package
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
ESD
Rating
−0.3 V to +3 V
−0.3 V to +6 V
−0.3 V to +3 V
−0.3 V to +3 V
−0.3 V to +6 V
−0.3 V to DVDD + 0.3 V
−0.3 V to +6 V
−0.3 V to AVDD4 + 0.3 V
−0.3 V to +0.3 V
±10 mA
−40°C to +85°C
−65°C to +150°C
150°C
92.7°C/W
5.1°C/W
215°C
220°C
600 V
1 Absolute maximum voltage on digital inputs is 3.0 V or DVDD + 0.3 V,
whichever is lower.
2 Absolute maximum voltage on VREF input is 6.0 V or AVDD4 + 0.3 V,
whichever is lower.
3 Transient currents of up to 200 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 28

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AD7762 pdf, datenblatt
AD7762
4500
4000
3500
3000
2500
2000
1500
1000
500
0
8385222
8385238
8385254
24-BIT CODE
8385270
Figure 17. Normal Mode, 24-Bit Histogram, 256× Decimation
0.0010
0.0005
+85°C
+25°C
0
–0.0005
–40°C
–0.0010
0
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
0
4194304
8388608
24-BIT CODE
12582912
Figure 18. 24-Bit INL, Normal Mode
16777216
4194304
8388608
24-BIT CODE
12582912
Figure 19. 24-Bit DNL
16777216
3000
2500
2000
1500
1000
500
0
8383530 83835246 8383562 8383578 8383594 8383610
24-BIT CODE
Figure 20. Low Power, 24-Bit Histogram, 256× Decimation
0.0015
0.0010
+85°C
0.0005
+25°C
0
–0.0005
–40°C
–0.0010
0
4194304
8388608
24-BIT CODE
12582912
Figure 21. 24-Bit INL, Low Power Mode
16777216
Rev. 0 | Page 12 of 28

12 Page





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