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PDF ADSP-BF544 Data sheet ( Hoja de datos )
| Número de pieza | ADSP-BF544 | |
| Descripción | (ADSP-BF54x) Embedded Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a•
Preliminary Technical Data
Blackfin®
Embedded Processor
ADSP-BF542/BF544/BF548/BF549
FEATURES
Up to 600 MHz High-Performance Blackfin Processor
Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs
RISC-Like Register and Instruction Model
0.8 V to TBD V Core VDD with On-chip Voltage Regulation
2.5 V and 3.3 V-Tolerant I/O with Specific 5 V-Tolerant Pins
400-ball Lead-Free mBGA Package
MEMORY
Up to 324K bytes of on-chip memory comprised of:
Instruction SRAM/cache; instruction SRAM;
data SRAM/cache; additional dedicated data SRAM;
scratchpad SRAM (see Table 1 on Page 3 for available
memory configurations
External Sync Memory Controller Supporting
DDR/Mobile DDR SDRAM
External Async Memory Controller Supporting 8/16 bit Async
Memories and Burst Flash Devices
NAND Flash Controller
Four Memory-to-Memory DMA pairs, two with external
requests
Memory Management Unit Providing Memory Protection
Flexible Booting Options
Code Security with LockboxTM Secure Technology
One-Time-Programmable (OTP) Memory
PERIPHERALS
High-Speed USB On-the-Go (OTG) with Integrated PHY
SD/SDIO Controller
ATA/ATAPI-6 Controller
Up to Four Synchronous Serial Ports (SPORTs)
Up to Three Serial Peripheral Interfaces (SPI-Compatible)
Up to Four UARTs, Two with Automatic Hardware Flow
Control
Up to Two CAN (Controller Area Network) 2.0B Interfaces
Up to Two TWI (Two-Wire Interface) Controllers
8- or 16-Bit Asynchronous Host DMA Interface
Multiple Enhanced Parallel Peripheral Interfaces (PPI), Sup-
porting ITU-R BT.656 Video Formats and 18/24-bit LCD
Connections
Media Transceiver (MXVR) for connection to a MOST®
Network
Pixel Compositor for overlays, alpha blending, and color
conversion
Up to Eleven 32-Bit Timers/Counters with PWM Support
Real-Time Clock (RTC) and Watchdog Timer
Up/Down Counter With Support for Rotary Encoder
Up to 152 General Purpose I/O (GPIOs)
On-Chip PLL Capable of 1x to 63x Frequency Multiplication
Debug/JTAG Interface
CAN (0-1)
TWI (0-1)
TIMERS(0-10)
COUNTER
KEYPAD
PAB 16
VOLTAGE
REGULATOR
JTAG TEST AND
EMULATION
RTC
B
WATCHDOG
TIMER
OTP
INTERRUPTS
L2
SRAM
L1
INSTR ROM
L1
INSTR SRAM
L1
DATA SRAM
HOST
UART (0-1)
UART (2-3)
SPI (0-1)
MXVR
USB
DCB 32
BOOT
ROM
EAB 64
DEB 32
EXTERNAL PORT
NOR, DDR1 CONTROL
DDR1
16
ASYNC
16
32-BIT DMA
16-BIT DMA
DAB32 32
DAB16 16
ATAPI
NAND FLASH
CONTROLLER
SPI (2)
SPORT (2-3)
SPORT (0-1)
SD / SDIO
EPPI (0-2)
PIXEL
C OM PO SITOR
Figure 1. Functional Block Diagram
• Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/461-3113 © 2006 Analog Devices, Inc. All rights reserved.
1 page  
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Preliminary Technical Data
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
ADSP-BF54x
ADDRESS ARITHMETIC UNIT
DA1 32
DA0 32
I3 L3 B3
I2 L2 B2
I1 L1 B1
I0 L0 B0
M3
M2
M1
M0
DAG1
32
RAB
DAG0
SP
FP
P5
P4
P3
P2
P1
P0
32
PREG
SD 32
LD1 32
LD0 32
32
32
R7.H
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
R7.L
R6.L
R5.L
R4.L
R3.L
R2.L
R1.L
R0.L
8
BARREL
SHIFTER
16
40
A0
88
40 40
32 32
DATA ARITHMETIC UNIT
ASTAT
16
8
40
A1
SEQUENCER
ALIGN
DECODE
LOOP BUFFER
CONTROL
UNIT
Figure 2. Blackfin Processor Core
MEMORY ARCHITECTURE
The ADSP-BF54x processor views memory as a single unified
4G byte address space, using 32-bit addresses. All resources,
including internal memory, external memory, and I/O control
registers, occupy separate sections of this common address
space. The memory portions of this address space are arranged
in a hierarchical structure to provide a good cost/performance
balance of some very fast, low-latency on-chip memory as cache
or SRAM, and larger, lower-cost and performance off-chip
memory systems. See Figure 3 on Page 6.
The on-chip L1 memory system is the highest-performance
memory available to the Blackfin processor. The off-chip mem-
ory system, accessed through the external bus interface unit
(EBIU), provides expansion with flash memory, SRAM, and
double-rate SDRAM (DDR1), optionally accessing up to
516M bytes of physical memory.
The ADSP-BF54x processor also includes an L2 SRAM memory
array which provides 128K bytes of high speed SRAM operating
at one half the frequency of the core, and slightly longer latency
than the L1 memory banks. The L2 memory is a unified instruc-
tion and data memory and can hold any mixture of code and
data required by the system design. The Blackfin cores share a
dedicated low latency 64-bit wide data path port into the L2
SRAM memory.
Rev. PrD | Page 5 of 64 | November 2006
5 Page 
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Preliminary Technical Data
The 32.768 KHz input clock frequency is divided down to a
1 Hz signal by a prescaler. The counter function of the timer
consists of four counters: a 60-second counter, a 60-minute
counter, a 24-hour counter, and an 32,768-day counter.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day. The second alarm is for a day and time of that
day.
The stopwatch function counts down from a programmed
value, with one-second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like the other peripherals, the RTC can wake up the
ADSP-BF54x processor from sleep mode upon generation of
any RTC wakeup event. Additionally, an RTC wakeup event can
wake up the ADSP-BF54x processor from deep sleep mode, and
wake up the on-chip internal voltage regulator from the hiber-
nate operating mode.
Connect RTC pins RTXI and RTXO with external components
as shown in Figure 4.
RTXI
RTXO
R1
X1
C1 C2
SUGGESTED COMPONENTS:
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)
EPSON MC405 12 PF LOAD (SURFACE MOUNT PACKAGE)
C1 = 22 PF
C2 = 22 PF
R1 = 10 M⍀
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF.
Figure 4. External Components for RTC
WATCHDOG TIMER
The ADSP-BF54x processor includes a 32-bit timer that can be
used to implement a software watchdog function. A software
watchdog can improve system availability by forcing the proces-
sor to a known state through generation of a hardware reset,
non-maskable interrupt (NMI), or general-purpose interrupt, if
the timer expires before being reset by software. The program-
mer initializes the count value of the timer, enables the
appropriate interrupt, then enables the timer. Thereafter, the
software must reload the counter before it counts to zero from
the programmed value. This protects the system from remain-
ing in an unknown state where software, which would normally
reset the timer, has stopped running due to an external noise
condition or software error.
ADSP-BF54x
If configured to generate a hardware reset, the watchdog timer
resets both the core and the ADSP-BF54x processor peripherals.
After a reset, software can determine if the watchdog was the
source of the hardware reset by interrogating a status bit in the
watchdog timer control register.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK.
TIMERS
There are up to two timer units in the ADSP-BF54x processors.
While one unit provides eight general-purpose programmable
timers, the other unit provide three of them. processors. Each
timer has an external pin that can be configured either as a Pulse
Width Modulator (PWM) or timer output, as an input to clock
the timer, or as a mechanism for measuring pulse widths and
periods of external events. These timers can be synchronized to
an external clock input to the several other associated PF pins,
an external clock input to the PPI_CLK input pin, or to the
internal SCLK.
The timer units can be used in conjunction with the two UARTs
and the CAN controller to measure the width of the pulses in
the data stream to provide a software auto-baud detect function
for the respective serial channels.
The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the general-purpose programmable timers,
another timer is also provided by the processor core. This extra
timer is clocked by the internal processor clock and is typically
used as a system tick clock for generation of operating system
periodic interrupts.
UP/DOWN COUNTER AND THUMBWHEEL
INTERFACE
A 32-bit up/down counter is provided that can sense 2-bit
quadrature or binary codes as typically emitted by industrial
drives or manual thumb wheels. The counter can also operate in
general-purpose up/down count modes. Then, count direction
is either controlled by a level-sensitive input pin or by two edge
detectors.
A third input can provide flexible zero marker support and can
alternatively be used to input the push-button signal of thumb
wheels. All three pins have a programmable debouncing circuit.
An internal signal forwarded to the timer unit enables one timer
to measure the intervals between count events. Boundary regis-
ters enable auto-zero operation or simple system warning by
interrupts when programmable count values are exceeded.
Rev. PrD | Page 11 of 64 | November 2006
11 Page | ||
| Páginas | Total 64 Páginas | |
| PDF Descargar | [ Datasheet ADSP-BF544.PDF ] | |
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