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PDF R2J20601NP Data sheet ( Hoja de datos )
| Número de pieza | R2J20601NP | |
| Descripción | Driver - MOSFET Integrated SiP | |
| Fabricantes | Renesas | |
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R2J20601NP
Driver – MOS FET Integrated SiP (DrMOS)
REJ03G0237-0500
Rev.5.00
Apr 10, 2006
Description
The R2J20601NP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in
a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this
device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap Schottky barrier
diode (SBD), eliminating the need for an external SBD for this purpose.
Integrating a driver and both high-side and low-side power MOS FETs, the new device is also compliant with the
package standard “Driver – MOS FET integrated SiP (DrMOS)” proposed by Intel Corporation.
Features
• Built-in power MOS FET suitable for applications with 12 V input and low output voltage
• Built-in driver circuit which matches the power MOS FET
• Built-in tri-state input function which can support a number of PWM controllers
• VIN operating-voltage range: 16 V max
• High-frequency operation (above 1 MHz) possible
• Large average output current (35 A)
• Achieve low power dissipation (About 5.6 W at 1 MHz, 25 A)
• Controllable driver: Remote on/off
• Built-in Schottky diode for bootstrapping
• Low-side drive voltage can be independently set
• Small package: QFN56 (8 mm × 8 mm × 0.8 mm)
Outline
VCIN BOOT
GH VIN
Reg5V
1
56
Driver
Tab
14
15
High-side MOS
Tab
DISBL#
PWM
MOS FET Driver
VSWH
Low-side MOS Tab
CGND VLDRV
GL PGND
43 28
42 29
(Bottom view)
QFN56 package 8 mm × 8 mm
Rev.5.00 Apr 10, 2006 page 1 of 13
1 page  
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R2J20601NP
Electrical Characteristics
(Ta = 25°C, VCIN = 12 V, VLDRV = 5 V, VSWH = 0 V, unless otherwise specified)
Item
Symbol Min Typ Max Units
Test Conditions
Supply
VCIN start threshold
VCIN shutdown threshold
UVLO hysteresis
VCIN bias current
VH
VL
dUVL
ICIN
VLDRV bias current
ILDRV
PWM
Input
5V
Regulator
PWM rising threshold
PWM falling threshold
PWM input resistance
Tri-state shutdown window
Shutdown hold-off time
Output voltage
Line regulation
VH-PWM
VL-PWM
RIN-PWM
VIN-SD
tHOLD-OFF
Vreg
Vreg-line
8.1 9.0 9.9
6.5 7.2 7.9
— 1.8 *1 —
10.5 14.0 18.5
31.5 40.7 46.5
3.5
0.9
30
VL-PWM
—
4.75
–10
3.8
1.2
50
—
240 *1
5.0
0
4.1
1.5
70
VH-PWM
—
5.25
10
V
V
V VH – VL
mA fPWM = 1 MHz,
ton-PWM = 125 ns
mA fPWM = 1 MHz,
ton-PWM = 125 ns
V
V
kΩ PWM = 1 V
V
ns
V
mV VCIN = 12 V to 16 V
Load regulation
Vreg-load –10
0
10 mV Ireg = 0 to 10 mA
DISBL# Disable threshold
VDISBL
0.9 1.2
Input
Enable threshold
VENBL
1.9 2.4
Input current
IDISBL
0.5 2.0
Note: 1. Reference values for design. Not 100% tested in production.
1.5
2.9
5.0
V
V
µA DISBL# = 1 V
Rev.5.00 Apr 10, 2006 page 5 of 13
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R2J20601NP
The PWM input is TTL level and has hysteresis. When the PWM input signal is abnormal, e.g., when the signal route
from the control IC is abnormal, the tri-state function turns off the high- and low-side MOS FETs. This function
operates when the PWM input signal stays in the input hysteresis window for 240 ns (typ.). After the tri-state mode has
been entered and GH and GL have become low, a PWM input voltage of 3.8 V or more is required to make the circuit
return to normal operation.
240 ns(tHOLD-OFF)
240 ns(tHOLD-OFF)
3.8 V
PWM 1.2 V
GH
GL
3.8 V
PWM 1.2 V
240 ns(tHOLD-OFF)
240 ns(tHOLD-OFF)
GH
GL
Figure 1
Rev.5.00 Apr 10, 2006 page 11 of 13
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet R2J20601NP.PDF ] | |
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