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ADSP-BF549 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP-BF549
Beschreibung (ADSP-BF54x) Embedded Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADSP-BF549 Datasheet, Funktion
www.DataSheet4U.com
a
Preliminary Technical Data
Blackfin®
Embedded Processor
ADSP-BF542/BF544/BF548/BF549
FEATURES
Up to 600 MHz High-Performance Blackfin Processor
Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs
RISC-Like Register and Instruction Model
0.8 V to TBD V Core VDD with On-chip Voltage Regulation
2.5 V and 3.3 V-Tolerant I/O with Specific 5 V-Tolerant Pins
400-ball Lead-Free mBGA Package
MEMORY
Up to 324K bytes of on-chip memory comprised of:
Instruction SRAM/cache; instruction SRAM;
data SRAM/cache; additional dedicated data SRAM;
scratchpad SRAM (see Table 1 on Page 3 for available
memory configurations
External Sync Memory Controller Supporting
DDR/Mobile DDR SDRAM
External Async Memory Controller Supporting 8/16 bit Async
Memories and Burst Flash Devices
NAND Flash Controller
Four Memory-to-Memory DMA pairs, two with external
requests
Memory Management Unit Providing Memory Protection
Flexible Booting Options
Code Security with LockboxTM Secure Technology
One-Time-Programmable (OTP) Memory
PERIPHERALS
High-Speed USB On-the-Go (OTG) with Integrated PHY
SD/SDIO Controller
ATA/ATAPI-6 Controller
Up to Four Synchronous Serial Ports (SPORTs)
Up to Three Serial Peripheral Interfaces (SPI-Compatible)
Up to Four UARTs, Two with Automatic Hardware Flow
Control
Up to Two CAN (Controller Area Network) 2.0B Interfaces
Up to Two TWI (Two-Wire Interface) Controllers
8- or 16-Bit Asynchronous Host DMA Interface
Multiple Enhanced Parallel Peripheral Interfaces (PPI), Sup-
porting ITU-R BT.656 Video Formats and 18/24-bit LCD
Connections
Media Transceiver (MXVR) for connection to a MOST®
Network
Pixel Compositor for overlays, alpha blending, and color
conversion
Up to Eleven 32-Bit Timers/Counters with PWM Support
Real-Time Clock (RTC) and Watchdog Timer
Up/Down Counter With Support for Rotary Encoder
Up to 152 General Purpose I/O (GPIOs)
On-Chip PLL Capable of 1x to 63x Frequency Multiplication
Debug/JTAG Interface
CAN (0-1)
TWI (0-1)
TIMERS(0-10)
COUNTER
KEYPAD
PAB 16
VOLTAGE
REGULATOR
JTAG TEST AND
EMULATION
RTC
B
WATCHDOG
TIMER
OTP
INTERRUPTS
L2
SRAM
L1
INSTR ROM
L1
INSTR SRAM
L1
DATA SRAM
HOST
UART (0-1)
UART (2-3)
SPI (0-1)
MXVR
USB
DCB 32
BOOT
ROM
EAB 64
DEB 32
EXTERNAL PORT
NOR, DDR1 CONTROL
DDR1
16
ASYNC
16
32-BIT DMA
16-BIT DMA
DAB32 32
DAB16 16
ATAPI
NAND FLASH
CONTROLLER
SPI (2)
SPORT (2-3)
SPORT (0-1)
SD / SDIO
EPPI (0-2)
PIXEL
C OM PO SITOR
Figure 1. Functional Block Diagram
• Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/461-3113 © 2006 Analog Devices, Inc. All rights reserved.






ADSP-BF549 Datasheet, Funktion
www.DataSheet4U.com
ADSP-BF54x
The memory DMA controllers (DMAC1 and DMAC0) pro-
vides high-bandwidth data-movement capability. They can
perform block transfers of code or data between the internal
memory and the external memory spaces.
0xFFFF FFFF
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA2 4000
0xFFA1 4000
0xFFA1 0000
0xFFA0 C000
0xFFA0 8000
0xFFA0 0000
0xFF90 8000
0xFF90 4000
0xFF90 0000
0xFF80 8000
0xFF80 4000
0xFF80 0000
0xFEB2 0000
0xFEB0 0000
0xEF00 1000
0xEF00 0000
0x3000 0000
0x2C00 0000
0x2800 0000
0x2400 0000
0x2000 0000
TOP OF LAST
DDR PAGE
0x0000 0000
CORE MMR REGISTERS (2M BYTE)
SYSTEM MMR REGISTERS (2M BYTE)
RESERVED
SCRATCHPAD SRAM (4K BYTE)
RESERVED
L1 ROM (64K BYTE)
INSTRUCTION SRAM / CACHE (16K BYTE)
RESERVED
INSTRUCTION BANK B SRAM (16K BYTE)
INSTRUCTION BANK A SRAM (32K BYTE)
RESERVED
DATA BANK B SRAM / CACHE (16K BYTE)
DATA BANK B SRAM (16K BYTE)
RESERVED
DATA BANK A SRAM / CACHE (16K BYTE)
DATA BANK A SRAM (16K BYTE)
RESERVED
L2 SRAM (128K BYTE)
RESERVED
BOOT ROM (4K BYTE)
RESERVED
ASYNC MEMORY BANK 3 (64M BYTE)
ASYNC MEMORY BANK 2 (64M BYTE)
ASYNC MEMORY BANK 1 (64M BYTE)
ASYNC MEMORY BANK 0 (64M BYTE)
RESERVED
DDR1 MEM BANK 1 (8M BYTE - 256M BYTE)
DDR1 MEM BANK 0 (8M BYTE - 256M BYTE)
Figure 3. ADSP-BF549 Internal/External Memory Map1
1 This memory map applies to all ADSP-BF54x processors, except for L2 memory
population. For details, see Table 1.
Internal (On-Chip) Memory
The ADSP-BF54x processor has several blocks of on-chip mem-
ory providing high-bandwidth access to the core.
The first block is the L1 instruction memory, consisting of
48K bytes SRAM, and also 16K bytes that can be configured as a
four-way set-associative cache or SRAM. This memory is
accessed at full processor speed.
The second on-chip memory block is the L1 data memory, con-
sisting of 64K bytes SRAM, of which 32K bytes can be
configured as a two-way set associative cache. This memory
block is accessed at full processor speed.
Preliminary Technical Data
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
The fourth memory block is the factory programmed L1
instruction ROM, operating at full processor speed. This ROM
is not customer configurable.
The fifth memory block is the L2 SRAM, providing 128K bytes
of unified Instruction and data memory, operating at one half
the frequency of the core.
Finally, there is a 4K boot ROM that can be seen as L3 memory.
It operates at full SCLK rate.
External (Off-Chip) Memory
Through the External Bus Interface Unit (EBIU) the
ADSP-BF54x processors provide glueless connectivity to exter-
nal 16-bit wide memories, such as DDR SDRAM, Mobile DDR,
SRAM, NOR flash, NAND flash, and FIFO devices. To provide
the best performance, the bus system of the DDR interface is
completely separate from the other parallel interfaces.
The DDR memory controller can gluelessly manage up to two
banks of double-rate synchronous dynamic memory (DDR1
SDRAM). The 16-bit wide interface operates at SCLK frequency
enabling maximum throughput of 532 Mbyte/s. The DDR or
Mobile DDR controller is augmented with a queuing mecha-
nism that performs efficient bursts onto the DDR. The
controller is an industry standard DDR SDRAM controller with
each bank supporting from 64 Mbit to 512 Mbit device sizes and
4-, 8-, or 16-bit widths. The controller supports up to 512
Mbytes in one bank, but the total in two banks is limited to 512
Mbytes. Each bank is independently programmable and is con-
tiguous with adjacent banks regardless of the sizes of the
different banks or their placement.
Traditional 16-bit asynchronous memories, such as SRAM,
EPROM, and flash devices, can be connected to one of the four
64 MByte asynchronous memory banks, represented by four
memory select strobes. Alternatively, these strobes can function
as bank-specific read or write strobes preventing further glue
logic when connecting to asynchronous FIFO devices.
In addition, the external bus can connect to advanced flash
device technologies, such as:
• Page-mode NOR flash devices
• Synchronous burst-mode NOR flash devices
• NAND flash devices
NAND Flash Controller (NFC)
The ADSP-BF54x provides a NAND Flash Controller (NFC) as
part of the external bus interface. NAND flash devices provide
high-density, low-cost memory. However, NAND flash devices
also have long random access times, invalid blocks, and lower
reliability over device lifetimes. Because of this, NAND flash is
often used for read-only code storage. In this case, all DSP code
can be stored in NAND flash and then transferred to a faster
memory (such as DDR or SRAM) before execution. Another
common use of NAND flash is for storage of multimedia files or
other large data segments. In this case, a software file system
Rev. PrD | Page 6 of 64 | November 2006

6 Page









ADSP-BF549 pdf, datenblatt
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ADSP-BF54x
SERIAL PORTS (SPORTS)
The ADSP-BF54x processor incorporates four dual-channel
synchronous serial ports (SPORT0, SPORT1, SPORT2,
SPORT3) for serial and multiprocessor communications. The
SPORTs support the following features:
• I2S capable operation.
• Bidirectional operation. Each SPORT has two sets of inde-
pendent transmit and receive pins, enabling eight channels
of I2S stereo audio.
• Buffered (8-deep) transmit and receive ports. Each port has
a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
• Clocking. Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
• Word length. Each SPORT supports serial data words from
3 to 32 bits in length, transferred most-significant-bit first
or least-significant-bit first.
• Framing. Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulsewidths and early or late
frame sync.
• Companding in hardware. Each SPORT can perform
A-law or μ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
• DMA operations with single-cycle overhead. Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
• Interrupts. Each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.
• Multichannel capability. Each SPORT supports 128 chan-
nels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
The ADSP-BF54x processor has three SPI-compatible ports that
allow the processor to communicate with multiple SPI-compati-
ble devices.
Each SPI port uses three pins for transferring data: two data pins
(master output-slave input, MOSI, and master input-slave out-
put, MISO) and a clock pin (serial clock, SCK). An SPI chip
select input pin (SPISS) lets other SPI devices select the proces-
sor, and seven SPI chip select output pins (SPISEL7–1) let the
processor select other SPI devices. The SPI select pins are recon-
figured programmable flag pins. Using these pins, the SPI ports
provide a full-duplex, synchronous serial interface, which sup-
ports both master/slave modes and multimaster environments.
Preliminary Technical Data
The SPI port’s baud rate and clock phase/polarities are pro-
grammable, and it has an integrated DMA controller,
configurable to support transmit or receive data streams. The
SPI’s DMA controller can only service unidirectional accesses at
any given time.
The SPI port’s clock rate is calculated as:
SPI Clock Rate = 2-----×----f-SS--P--C--I--_L---BK---a---u---d--
Where the 16-bit SPI_BAUD register contains a value of 2 to
65,535.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam-
pling of data on the two serial data lines.
UART PORTS (UARTS)
The ADSP-BF54x processor provides four full-duplex Universal
Asynchronous Receiver/Transmitter (UART) ports. Each
UART port provides a simplified UART interface to other
peripherals or hosts, supporting full-duplex, DMA-supported,
asynchronous transfers of serial data. A UART port includes
support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or
odd parity. Each UART port supports two modes of operation:
• PIO (programmed I/O). The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA (Direct Memory Access). The DMA controller trans-
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. Each UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates. Flexi-
ble interrupt timing options are available on the transmit
side.
Each UART port's baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
• Supporting bit rates ranging from (fSCLK/ 1,048,576) to
(fSCLK) bits per second.
• Supporting data formats from 7 to12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The UART port’s clock rate is calculated as:
UART
Clock Rate
=
------------------------------f--S---C----L----K--------------------------------
16(1 EBIO) × UART_Divisor
Where the 16-bit UART Divisor comes from the UARTx_DLH
register (most significant 8 bits) and UARTx_DLL register (least
significant 8 bits).
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
Rev. PrD | Page 12 of 64 | November 2006

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