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W25B40A Schematic ( PDF Datasheet ) - Winbond

Teilenummer W25B40A
Beschreibung 4M-BIT SERIAL FLASH MEMORY
Hersteller Winbond
Logo Winbond Logo 




Gesamt 30 Seiten
W25B40A Datasheet, Funktion
www.DataSheet4U.com
W25B40/W25B40A
4M-BIT SERIAL FLASH MEMORY
WITH BOOT AND PARAMETER SECTORS
Formally NexFlash NX25B40
The Winbond W25B40 / W25B40A is fully compatible with the previous NexFlash NX25B40 Serial
Flash memory.
Publication Release Date: January 6, 2006
- 1 - Revision M






W25B40A Datasheet, Funktion
W25B40/W25B40A
4.3 Serial Data Output (DO)
The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from
(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.
4.4 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP2, BP1 and BP0) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The /WP pin is
active low.
4.5 Hold (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought
low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be
ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function
can be useful when multiple devices are sharing the same SPI signals. (“See Hold function”)
4.6 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI "Operations")
4.7 Serial Data Input (DI)
The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be serially
written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK) input
pin.
-6-

6 Page









W25B40A pdf, datenblatt
W25B40/W25B40A
8.1.6 Write Protection Operation - Bottom Boot Sector Organization
STATUS REGISTER
BP2 BP1 BP0
11
1
11
0
10
1
10
0
01
1
01
0
00
1
00
0
W25B40 / W25B40A (4M-BIT) MEMORY PROTECTION
SECTOR(S)
ADDRESSES
DENSITY (KB)
PORTION
ALL 000000h - 07FFFFh
512KB
ALL
0 thru 7
000000h - 03FFFFh
256KB
Lower 1/2
0 thru 4
000000h - 00FFFFh
64KB
Lower 1/8
0 thru 3
000000h - 007FFFh
32KB
Lower 1/16
0 thru 2
000000h - 003FFFh
16KB
Lower 1/32
0 thru 1
000000h - 001FFFh
8KB Lower 1/64
0 000000h - 000FFFh
4KB Lower 1/128
NONE
NONE
NONE
NONE
8.1.7 Write Protection Operation - Top Boot Sector Organization (Special Order)
STATUS REGISTER
BP2 BP1 BP0
00
0
00
1
01
0
01
1
10
0
10
1
11
0
11
1
W25B40 / W25B40A (4M-BIT) MEMORY PROTECTION
SECTOR(S)
ADDRESSES
DENSITY (KB)
PORTION
NONE
NONE
NONE
NONE
11 07F000h - 07FFFFh
4KB Upper 1/128
10 thru 11 07E000h - 07FFFFh
8KB Upper 1/64
9 thru 11
07C000h - 07FFFFh
16KB
Upper 1/32
8 thru 11
078000h - 07FFFFh
32KB
Upper 1/16
7 thru 11
070000h - 07FFFFh
64KB
Upper 1/8
4 thru 11
040000h - 07FFFFh
256KB
Upper 1/2
ALL 000000h - 07FFFFh
512KB
ALL
8.2 INSTRUCTIONS
The instruction set of the W25B40 / W25B40A consists of twelve basic instructions that are fully
controlled through the SPI bus (see Instruction Set table). Instructions are initiated with the falling
edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code.
Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes,
data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed
with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in
figures 4 through 17. All read instructions can be completed after any clocked bit. However, all
instructions that Write, Program or Erase must complete on a byte boundary (/CS) driven high after a
full 8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects
the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or
when the Status Register is being written, all instructions except for Read Status Register will be
ignored until the program or erase cycle has completed.
- 12 -

12 Page





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