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PDF ADS-325A Data sheet ( Hoja de datos )
| Número de pieza | ADS-325A | |
| Descripción | Sampling A/D Converter | |
| Fabricantes | Datel | |
| Logotipo |  |
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®
®
INN O VAT IO N a n d E X C E L L E N C E
FEATURES
• 10-bit, 20MHz sampling
• ±1LSB max. differential nonlinearity
• Internal calibration circuit
• Internal S/H amplifier
• 70MHz input bandwidth
• TTL/CMOS compatible in-out logic
• Latched three-state output data
• Single +5V supply
• Low 150mW power dissipation
• Small 48 pin LQFP package
• Low cost
GENERAL DESCRIPTION
DATEL's ADS-325A is a low power, 10-bit, 20MHz, CMOS
sampling A/D converter. Its small 48 pin plastic LQFP package
contains a S/H amplifier, a 3-state output register, linearity
calibration circuitry, and all necessary control logic. Only two
external reference voltages, an A/D clock and a few digital
inputs are required. The A/D clock may be applied with 50%
duty cycle.
The excellent dynamic performance includes a spurious free
dynamic range of 65dB and a signal-to-noise ratio with
distortion of 54dB with a 3MHz input. ADS-325A is capable of
operating from a single +5V power supply and typically
consumes only 150mW. It can also operate from a +5V analog
VS with +3.3V digital VS enabling an interface with 3.3V logic
circuitry. The ADS-325A is ideally suited for high quality video/
CCD imaging applications.
ADS-325A
10-Bit, 20MHz
Sampling A/D Converter
INPUT/OUTPUT CONNECTIONS
PIN FUNCTION
1 BIT 10 (LSB)
2 BIT 9
3 BIT 8
4 BIT 7
5 BIT 6
6 DIGITAL GROUND (DGND)
7 +DVS (Digital)
8 BIT 5
9 BIT 4
10 BIT 3
11 BIT 2
12 BIT 1 (MSB)
13 TEST PIN
14 TEST SIGNAL IN
15 RESET
16 DIGITAL GROUND (DGND)
17 SELECT (SEL)
18 +AVS (Analog)
19 TEST MODE
20 LINV
21 MINV
22 A/D CLOCK
23 OUTPUT ENABLE (OE)
24 CHIP ENABLE (CE)
PIN FUNCTION
48 DIGITAL GROUND (DGND)
47 NO CONNECTION
46 NO CONNECTION
45 +DVS (Digital)
44 ANALOG GROUND (AGND)
43 ANALOG GROUND (AGND)
42 TEST SIGNAL IN
41 CALIBRATION (CAL)
40 NO CONNECTION
39 ANALOG INPUT (VIN)
38 TEST SIGNAL OUT
37 TEST SIGNAL IN
36 ANALOG GROUND (AGND)
35 REFERENCE BOTTOM (VRB)
34 REFERENCE BOTTOM (VRB)
33 NO CONNECTION
32 NO CONNECTION
31 NO CONNECTION
30 REFERENCE TOP (VRT)
29 REFERENCE TOP (VRT)
28 ANALOG GROUND (AGND)
27 ANALOG GROUND (AGND)
26 +AVS (Analog)
25 +AVS (Analog)
AGND
+AVS
44
43
27
28
36
18
25
26
VIN 39
VRT 29
VRT 30
VRB 34
VRB 35
SENSE
AMP
#1
S/H AMP
COARSE
COMPARISON
AND
ENCODE
A/D CLOCK 22
CE 24
OE 23
TIMING GEN.
+ x8
COARSE
CORRECTION
AND
LATCH
DAC
CALIBRATION
UNIT
FINE
COMPARISON
AND
ENCODE
FINE
LATCH
SENSE
AMP
#2
AUTOCALIBRATION
PULSE
GENERATOR
12 BIT 1 (MSB)
11 BIT 2
10 BIT 3
9 BIT 4
8 BIT 5
5 BIT 6
4 BIT 7
3 BIT 8
2 BIT 9
1 BIT 10 (LSB)
21 MINV
20 LINV
19 TEST MODE
41 CAL
17 SEL
15 RESET
Figure 1. ADS-325A Functional Block Diagram
DATEL, Inc., Mansfield, MA 02048 (USA) • Tel: (508) 339-3000, (800) 233-2765 Fax: (508) 339-6356 • Email: [email protected] • Internet: www.datel.com
1 page  
®®
ADS-325A
Re-initiating the Start-up Calibration
The start-up calibration function can be re-initiated at any time
desired after the power and the references are supplied. Apply
a positive pulse to CE pin (pin 24) or a negative pulse to
RESET pin (pin 15). The pulse width of these pulses must be
equal to or wider than one A/D clock cycle. Also due to this
feature, you can make sure of a proper start-up calibration at
power-up by making a C-R delay connection with the RESET
pin as shown in Figure 4c.
Using Start-up Calibration Function Only
Internal and external calibration functions need not be
employed after start-up calibration. To use only the start-up
calibration function, connect the SEL pin (pin 17) to AGND and
the CAL pin (pin 14) to +AVS or AGND.
Auto Calibration Function
After the start up calibration is completed, the internal
calibration function can periodically and automatically generate
calibration pulses when the auto calibration mode is enabled.
To enable this function connect the SEL pin (pin 17) and the
CAL pin (pin 41) to +AVS. In this mode a 24-bit counter is
counted with every 16 A/D clock cycles and the carry-out is
used as the calibration pulse. The period of the calibration
pulse generated is as follows:
Period of Auto-calibration pulse = 1/fCLK x 16 x 16,777,216
For the case when the A/D clock frequency is 14.3MHz, the
calibration pulse generation cycle is 18.8 seconds. Since a
single calibration process is performed once every seven
pulses, the total calibration cycle is approximately
132 seconds.
A/D CLOCK
1/16
+AVS
14-BIT COUNTER
CO
CLR
DQ
CLR
OUT
+AVS
AGND
VRT
VRB
RESET
CE
SENSE
AMP #1
SENSE
AMP #2
24-BIT COUNTER
CO
CLR
SEL
CAL
Figure 4a Internal Calibration Pulse Generation Circuit
VOLTS
+5
1V
+2.5
+AVS
VRT
VRB
0 TIME
SENSE AMP #1
SENSE AMP #2
CLR
RESET = HIGH, CE = LOW
Figure 4b. Conditions for Start-Up Calibration
+AVS
5V
15
+AVS
VRT
RESET
VRB
CE = "L"
Figure 4c. Start-up Calibration using RESET
T PW1
T PW0
CLOCK
+1.65V
Tsd
ANALOG
INPUT
N
TDL
OUTPUT
DATA
N+1
N–3
N+2
N–2
N+3
N–1
+1.65V (+DVS = +3.3V)
+2.5V (+DVS = +5.0V)
OUTPUT
N+4 ENABLE (OE)
OUTPUT
N
DATA
ACTIVE
TPEZ
TPZE
HIGH IMPEDENCE
+1.65V (+DVS = +3.3V)
+2.5V (+DVS = +5.0V)
= SAMPLING POINT
Figure 5. ADS-325A Timing Diagrams
+1.65V (+DVS = +3.3V)
+2.5V (+DVS = +5.0V)
ACTIVE
5
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| PDF Descargar | [ Datasheet ADS-325A.PDF ] | |
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