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DP83231 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer DP83231
Beschreibung CRD Device
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 16 Seiten
DP83231 Datasheet, Funktion
www.DataSheet4U.com
February 1991
DP83231 CRDTM Device
(FDDI Clock Recovery Device)
General Description
The DP83231 CRD device is a clock recovery device that
has been designed for use in 100 Mbps FDDI (Fiber Distrib-
uted Data Interface) networks The device receives serial
data from a Fiber Optic Receiver in differential ECL NRZI
4B 5B group code format and outputs resynchronized NRZI
received data and a 125 MHz received clock in differential
ECL format for use by the DP83251 55 PLAYERTM device
Features
Y Clock recovery at 100 Mbps data rate
Y Internal 250 MHz VCO
0 1% VCO operating range
Crystal controlled
Y Precision window centering delay line
Y Single a5V supply
Y 28-pin PLCC package
Y BiCMOS processing
FIGURE 1-1 FDDI Chip Set Block Diagram
TL F 10384 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
BSITM BMACTM PLAYERTM CDDTM and CRDTM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 10384
RRD-B30M105 Printed in U S A






DP83231 Datasheet, Funktion
3 0 Pin Descriptions
Symbol
DATAa
DATAb
LBDa
LBDb
ELB
CLK DET
CRD EN
OSC FLTRa
OSC FLTRb
DIF AMP
OUT
OSC IN
OSC OUT
RXCa
RXCb
RXDa
RXDb
VCO FLTR
SDa
SDb
TTLSD
TEST EN
DVCC
Pin No
8
9
25
24
4
6
7
23
22
21
20
19
3
2
27
26
13
18
17
5
10
16
I O Description
I DATAg 4B 5B serial NRZI data inputs originating from a fiber optic receiver and presented for
the purpose of resynchronization and clock recovery These differential 100k ECL compatible
inputs are selected when the ELB input is at a logic Low level
I Loopback Datag 4B 5B serial NRZI data inputs originating from a local PLAYER device and
presented for the purpose of station diagnostics These differential 100k ECL compatible inputs
are selected when the ELB input is at a logic High level
I Enable Loopback TTL compatible input which selects between the DATA g inputs or the LBD
g inputs The LBD inputs are selected when the ELB pin is at a logic High level and the DATA
inputs when at a logic Low level
O Clock Detect CMOS output used to indicate that the chip has detected the presence of a
continuous data frequency greater than 3 0 MHz A logic High level on the output will indicate that
valid input data has been detected
I CRD Enable TTL compatible input which directs the differential charge pump outputs to either
operate the crystal oscillator at the center of its operating range or to track out the VCO phase
errors in the second PLL The CRD EN input will reset the CLK DET function and will force the
oscillator to the center of its operating range when at a logic LOW level and will allow normal PLL
tracking operation when at a logic High level Deassertion of the CRD EN input will momentarily
stop the VCO
O Oscillator Filterg The differential charge pump up and down outputs which are part of the
second PLL A three element filter should be connected to each of these pins which consists of
one capacitor in parallel with a resistor and another capacitor to ground These outputs are driven
to their maximum upper operating level when the CRD EN pin is at a logic LOW level or when
valid data frequencies are not recognized at the data inputs
O Differential Amplifier Output The differential amplifier output associated with the second PLL
which is used to adjust the frequency of the external crystal
I Oscillator Input and Output The terminals for the crystal oscillator which require connection of
the crystal tank circuit varactors and capacitors
O Receive Clock Differential 100K ECL receive clock outputs which operate at 125 MHz
synchronized to the selected inputs (NRZI DATA g or LBD g) when valid line state data is
present When valid line state data is not present these outputs continue to operate at a nominal
frequency of 125 MHz g12 kHz These outputs should be terminated externally with a
conventional ECL 50X equivalent load
O Receive Data Differential 100K ECL received data outputs which provide a resynchronized
equivalent of the selected NRZI DATA or LBD inputs The received data output transitions occur
concurrent with the falling edge of the RXC g output These outputs should be terminated
externally with a conventional ECL 50X equivalent load
O VCO Filter Low pass filter associated with the first PLL A three element filter should be
connected to this pin which consists of one capacitor in parallel with a resistor and another
capacitor to ground
I Signal Detect Differential inputs to a 100K ECL to TTL translator intended for conversion of the
fiber optic receiver’s ECL signal detect to TTL for a player device The inputs are used in the test
modes as inputs for single stepping and gating the VCO
O TTL Signal Detect Intended to be a signal detect output in TTL format for use by the PLAYER
chip
I Test Enable CMOS input which enables the test functions This input must be at a logic low level
in normal operation
Digital VCC Positive power supply for most of the internal logic circuitry intended for a5V
operation g5% relative to ground Bypass capacitors should be placed as close as possible
across the DVCC and DGND pins DVCC AVCC and EXTVCC should be tied together through
chokes
6

6 Page









DP83231 pdf, datenblatt
5 0 Detailed Information (Continued)
5 3 INPUT AND OUTPUT SCHEMATICS
SDg
DATAg LBDg
DIF AMP
TL F 10384–11
OSC FLTR
TL F 10384 – 12
VCO FLTR
TL F 10384–13
OSCIN OSCOUT
TL F 10384 – 14
TL F 10384–15
12
TL F 10384 – 16

12 Page





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