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DS1863 Schematic ( PDF Datasheet ) - Maxim Integrated Products

Teilenummer DS1863
Beschreibung Burst Mode PON Controller
Hersteller Maxim Integrated Products
Logo Maxim Integrated Products Logo 




Gesamt 30 Seiten
DS1863 Datasheet, Funktion
www.DataSheet4U.com
Rev 0; 10/06
Burst-Mode PON Controller
With Integrated Monitoring
General Description
The DS1863 controls and monitors all the burst-mode
transmitter and video receiver biasing functions for a
passive optical network (PON) triplexer. It has an APC
loop with tracking-error compensation that provides the
reference for the laser-driver’s bias current, and a tem-
perature indexed lookup table (LUT) that controls the
modulation current. It continually monitors for high output
current, high bias current, and low and high transmit
power with its internal fast comparators to ensure that
laser shutdown for eye safety requirements are met with-
out adding external components. Five ADC channels
monitor VCC, internal temperature, and three external
monitor inputs (MON1–3) that can be used to meet trans-
mitter and receive monitoring requirements.
Applications
BPON, GPON and GEPON, Burst-Mode Transmitters
Laser Control and Monitoring
Broadband Local Access
Features
o Meets BPON, GPON, and GEPON Timing
Requirements for Burst-Mode Transceivers
o Bias Current Control provided by APC Loop with
Tracking Error Compensation
o Modulation Current is Controlled by a
Temperature-Indexed Lookup Table
o Supports 0dB, -3dB, -6dB Power Leveling
Settings with no Additional Calibration
o Internal Direct-to-Digital Temperature Sensor
o Five Analog Monitor Channels: Temperature, VCC,
MON1, MON2, and MON3
o Comprehensive Fault Management System with
Maskable Laser Shutdown Capability
o Two-Level Password Access to Protect
Calibration Data
o 120 Bytes of Password 1 (PW1) Protected
Nonvolatile Memory
o 128 Bytes of Password 2 (PW2) Protected
Nonvolatile Memory
o I2C-Compatible Interface for Calibration and
Monitoring
o Operating Voltage: 2.85V to 5.5V
o Operating Temperature: -40°C to +95°C
o 16-Pin Lead-Free TSSOP Package
Pin Configuration
TOP VIEW
+
BEN 1
TX-D 2
N.C. 3
TX-F 4
FETG 5
DS1863
SDA 6
SCL 7
GND 8
16 VCC
15 BMD
14 MOD
13 BIAS
12 GND
11 MON3
10 MON2
9 MON1
TSSOP
(173 mils)
Ordering Information
PART
DS1863E+
DS1863E+T&R
TEMP RANGE
-40°C to +95°C
-40°C to +95°C
+Denotes lead-free package.
T&R denotes tape-and-reel.
PIN-PACKAGE
16 TSSOP
16 TSSOP
______________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.






DS1863 Datasheet, Funktion
www.DataSheet4U.com
Burst-Mode PON Controller
With Integrated Monitoring
Pin Description
PIN NAME
DESCRIPTION
1 BEN Burst Enable Input. Triggers the sampling of the APC and Quick-trip monitors.
2 TX-D Transmit Disable Input. Disables BIAS and MOD outputs.
3 N.C. No Connection
4 TX-F Transmit Fault Output. Open-drain.
5 FETG Output to FET Gate. Signals an external N or P Channel MOSFET to enable/disable the lasers current.
6 SDA I2C Serial Data I/O
7 SCL I2C Serial Clock Input
8 GND Ground
9 MON1 External Analog Inputs. The voltage at these pins is digitized by the internal analog-to-digital converter
10 MON2 and can be read through the I2C interface. Alarm and warning values can be assigned to interrupt the
11 MON3 processor based on the ADC result.
12 GND Ground
13 BIAS Bias Current Output. This current DAC generates the bias current reference for the MAX3643.
14
MOD
Modulation Output Voltage. This 8-bit voltage output has 8 full-scale ranges from 1.25V to 0.3125V.
This pin is connected to the MAX3643s VMSET input to control the modulation current.
15 BMD Monitor Diode Input (Feedback Voltage, Transmit Power Monitor)
16 VCC Power Supply Input
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DS1863 pdf, datenblatt
www.DataSheet4U.com
Burst-Mode PON Controller
With Integrated Monitoring
used to prevent the alarms from triggering the TX-F and
FETG outputs. See below for more detail on the TX-F
and FETG outputs.
ADC Timing
There are five analog channels that are digitized in a
round robin fashion in the order shown in Figure 4. The
total time required to convert all five channels is tRR
(see electrical specifications for details).
Right Shifting A/D Conversion Result
If the weighting of the ADC digital reading must con-
form to a Predetermined Full-Scale (PFS) value defined
by a specification, then right shifting can be used to
adjust the PFS analog measurement range while main-
taining the weighting of the ADC results. The DS1863s
range is wide enough to cover all requirements; when
maximum input value is far short of the FS value, right
shifting can be used to obtain greater accuracy. For
instance, the maximum voltage might be 1/8 of the
specified PFS value, so only 1/8 of the converters
range is effective over this range. An alternative is to
calibrate the ADCs full scale range to 1/8 the readable
PFS value and use a right-shift value of 3. With this
implementation, the resolution of the measurement has
increased by a factor of 8, and because the result is
digitally divided by 8 by right shifting, the bit weight of
the measurement still meets the standard.
The right shift operation on the A/D converter results is
carried out based on the contents of Right Shift Control
Registers (Table 02h Registers 8Eh to 8Fh) in EEPROM.
Three analog channels: MON1 to MON3 each have 3
bits allocated to set the number of right shifts. Up to 7
right shift operations are allowed and will be executed
as a part of every conversion before the results are
compared to the high and low alarm levels, or loaded
into their corresponding measurement registers 62h to
69h. This is true during the setup of internal calibration
as well as during subsequent data conversions.
Transmit Fault (TX-F) Output
The TX-F output has masking registers for the five ADC
alarms and the four QT alarms to select which compar-
isons cause it to assert. In addition, the FETG alarm is
selectable via the TX-F mask to cause TX-F to assert.
All alarms, with the exception of FETG, will only cause
TX-F to remain active while the alarm condition persists.
However, the TX-F latch bit can enable the TX-F output
to remain active until it is cleared by the TX-F reset bit,
TX-D, soft TX-D, or by power cycling the part. If the
FETG output is configured to trigger TX-F, then it is indi-
cating that the DS1863 is in shutdown, and will require
TX-D, soft TX-D, or cycling power to reset. The ADC
and Quick-trip alarms (with the exception of BIAS MAX)
are ignored for the first 8-10 bias current updates dur-
ing power up. Only enabled alarms will activate TX-F.
The following table shows TX-F as a function of TX-D
and the alarm sources.
TX-F as a Function of TX-D and Alarm
Sources
VCC > VPOA
No
Yes
Yes
Yes
TX-D
X
0
0
1
NON-MASKED
TX-F ALARM
X
0
1
X
TX-F
1
0
1
0
Safety Shutdown (FETG) Output
The FETG output has masking registers (separate from
TX-F) for the five ADC alarms and the four QT alarms to
select which comparisons cause it to assert. Unlike TX-F,
NORMAL ADC SAMPLE TIMING
ONE ROUND-ROBIN ADC CYCLE
MON3
TEMP
VCC
MON1
MON2
MON3
TEMP
VCC
tRR
Figure 4. ADC Round-Robin Timing.
If VCC low alarm is set for either the TX-F or FETG output, the Round Robin timing will cycle between only TEMP and VCC.
12 ____________________________________________________________________

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