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DS26528 Schematic ( PDF Datasheet ) - Maxim Integrated Products

Teilenummer DS26528
Beschreibung Octal T1/E1/J1 Transceiver
Hersteller Maxim Integrated Products
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Gesamt 30 Seiten
DS26528 Datasheet, Funktion
www.DataSheet4U.com
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26528 is a single-chip 8-port framer and line
interface unit (LIU) combination for T1, E1, and J1
applications. Each port is independently configurable,
supporting both long-haul and short-haul lines.
APPLICATIONS
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
FUNCTIONAL DIAGRAM
T1/E1/J1
NETWORK
DS26528
T1/J1/E1
Transceiver
x8
BACKPLANE
TDM
DS26528
Octal T1/E1/J1 Transceiver
FEATURES
§ Eight Complete T1, E1, or J1 Long-Haul/Short-
Haul Transceivers (LIU plus Framer)
§ Independent T1, E1, or J1 Selections for Each
Transceiver
§ Internal Software-Selectable Transmit- and
Receive-Side Termination for 100W T1 Twisted
Pair, 110W J1 Twisted Pair, 120W E1 Twisted
Pair, and 75W E1 Coaxial Applications
§ Crystal-Less Jitter Attenuators can be Selected
for Transmit or Receive Path. The Jitter
Attenuator meets ETSI CTR 12/13, ITU G.736,
G.742, G.823, and AT&T PUB 62411.
§ External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
operation. This Clock is Internally Adapted for T1
or E1 Usage in the Host Mode.
§ Receive Signal Level Indication from -2.5dB to
-36dB in T1 Mode and -2.5dB to -44dB in E1
Mode in Approximate 2.5dB Increments
§ Transmit Open and Short Circuit Detection
§ LIU LOS in Accordance with G.775, ETSI
300233, and T1.231
§ Transmit Synchronizer
§ Flexible Signaling Extraction and Insertion Using
Either the System Interface or Microprocessor
Port
§ Alarm Detection and Insertion
§ T1 Framing Formats of D4, SLC-96, and ESF
§ J1 Support
§ E1 G.704 and CRC-4 Multiframe
§ T1 to E1 Conversion
Features continued in Section 2.
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS26528
-40°C to +85°C 256 TE-CSBGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 012405






DS26528 Datasheet, Funktion
DS26528 Octal T1/E1/J1 Transceiver
LIST OF TABLES
Table 4-1. T1-Related Telecommunications Specifications.................................................................... 12
Table 4-2. E1-Related Telecommunications Specifications ................................................................... 13
Table 8-1. Detailed Pin Descriptions...................................................................................................... 17
Table 9-1. Reset Functions.................................................................................................................... 26
Table 9-2. Registers Related to the Elastic Store .................................................................................. 30
Table 9-3. Elastic Store Delay After Initialization ................................................................................... 31
Table 9-4. Registers related to the IBO Multiplexer ............................................................................... 33
Table 9-5. RSER Output Pin Definitions ................................................................................................ 37
Table 9-6. RSIG Output Pin Definitions ................................................................................................. 37
Table 9-7. TSER Input Pin Definitions ................................................................................................... 38
Table 9-8. TSIG Input Pin Definitions..................................................................................................... 38
Table 9-9. RSYNC Input Pin Definitions ................................................................................................ 39
Table 9-10. D4 Framing Mode ............................................................................................................... 43
Table 9-11. ESF Framing Mode............................................................................................................. 43
Table 9-12. SLC-96 Framing ................................................................................................................. 44
Table 9-13. E1 FAS/NFAS Framing....................................................................................................... 45
Table 9-14. Registers Related to Setting Up the Framer ....................................................................... 46
Table 9-15. Registers Related to the Transmit Synchronizer ................................................................. 47
Table 9-16. Registers Related to Signaling............................................................................................ 48
Table 9-17. Registers Related to SLC96 ............................................................................................... 51
Table 9-18. Registers Related to T1 Transmit BOC............................................................................... 53
Table 9-19. Registers Related to T1 Receive BOC................................................................................ 53
Table 9-20. Registers Related to T1 Transmit FDL................................................................................ 54
Table 9-21. Registers Related to T1 Receive FDL................................................................................. 55
Table 9-22. Registers Related to Maintenance and Alarms ................................................................... 57
Table 9-23. T1 Alarm Criteria ................................................................................................................ 59
Table 9-24. T1 Line Code Violation Counting Options ........................................................................... 60
Table 9-25. E1 Line Code Violation Counting Options ........................................................................... 61
Table 9-26. T1 Path Code Violation Counting Arrangements................................................................. 61
Table 9-27. T1 Frames Out Of Sync Counting Arrangements................................................................ 62
Table 9-28. Registers Related to DS0 Monitoring.................................................................................. 62
Table 9-29. Registers Related to T1 In-Band Loop Code Generator...................................................... 64
Table 9-30. Registers Related to T1 In-Band Loop Code Detection....................................................... 65
Table 9-31. Register Related to Framer Payload Loopbacks................................................................. 66
Table 9-32. Registers Related to Control of DS26528 LIU..................................................................... 75
Table 9-33. The Telecommunications Specification Compliance for DS26528 Transmitters.................. 76
Table 9-34. Transformer Specifications ................................................................................................. 76
Table 9-35. T1.231, G.775, and ETSI 300 233 Loss Criteria Specifications........................................... 80
Table 9-36. Jitter Attenuator Standards Compliance.............................................................................. 82
Table 10-1. Register Address Ranges (in Hex)...................................................................................... 88
Table 10-2. Global Register List ............................................................................................................ 90
Table 10-3. Framer Register List ........................................................................................................... 90
Table 10-4. LIU Register List ................................................................................................................. 97
Table 10-5. BERT Register List ............................................................................................................. 97
Table 10-6. Global Register Bit Map...................................................................................................... 98
Table 10-7. Framer Register Bit Map..................................................................................................... 99
Table 10-8. LIU Register Bit Map......................................................................................................... 105
Table 10-9. BERT Register Bit Map..................................................................................................... 106
Table 10-10. Backplane Reference Clock Select................................................................................. 110
Table 10-11. Master Clock Input Selection .......................................................................................... 111
Table 10-12. Device ID Codes in this Product Family .......................................................................... 114
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DS26528 pdf, datenblatt
DS26528 Octal T1/E1/J1 Transceiver
4. SPECIFICATIONS COMPLIANCE
The DS26528 LIU meets all the latest relevant telecommunications specifications. Table 4-1 provides the T1 and
E1 specifications and relevant sections that are applicable to the DS26528.
Table 4-1. T1-Related Telecommunications Specifications
ANSI T1.102- Digital Hierarchy Electrical Interface.
AMI Coding.
B8ZS Substitution Definition.
DS1 Electrical Interface. Line rate +/- 32ppm; Pulse Amplitude between 2.4 to 3.6 V peak; Power Level between
12.6 to 17.9dbm; The T1 pulse mask is provided that we comply. DSX-1 for cross connects the return loss is
greater than -26dB. The DSX-1 cable is restricted up to 655 feet.
This specification also provides cable characteristics of DSX-Cross Connect cable ---22 AVG cables of 1000 feet.
ANSI T1.231- Digital Hierarchy- Layer 1 in Service Performance Monitoring
BPV Error Definition; Excessive Zero Definition; LOS description; AIS definition.
ANSI T1.403- Network and Customer Installation Interface- DS1 Electrical Interface
Description of the Measurement of the T1 Characteristics—100W. Pulse shape and template compliance
according to T1.102; Power level 12.4 to 19.7dbm when all ones is transmitted.
LBO for the Customer Interface (CI) is specified as 0dB, -7.5dB and -15dB. Line rate is +/-32 ppm. Pulse
Amplitude is 2.4 to 3.6V.
AIS generation as unframed all ones is defined.
The total cable attenuation is defined as 22dB. The DS26528 will function with up to -36dB cable loss.
Note that the pulse template defined by T1.403 and T1.102 are different --- specifically at Times .61, -.27, -34 and
.77. The DS26528 is complaint to both templates.
Pub 62411
This specification has tighter jitter tolerance and transfer characteristics than other specifications.
The jitter transfer characteristics are tighter than G.736 and Jitter Tolerance is tighter the G.823.
(ANSI) “Digital Hierarchy – Electrical Interfaces”
(ANSI) “Digital Hierarchy – Formats Specification”
(ANSI) “Digital Hierarchy – Layer 1 In-Service Digital Transmission Performance Monitoring”
(ANSI) “Network and Customer Installation Interfaces – DS1 Electrical Interface”
(AT&T) “Requirements for Interfacing Digital Terminal Equipment to Services Employing the Extended Super
frame Format”
(AT&T) “High Capacity Digital Service Channel Interface Specification”
(TTC) “Frame Structures on Primary and Secondary Hierarchical Digital Interfaces”
(TTC) “ISDN Primary Rate User-Network Interface Layer 1 Specification”
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