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EPM7128B Schematic ( PDF Datasheet ) - Altera Corporation

Teilenummer EPM7128B
Beschreibung (EPM7000B) Programmable Logic Device
Hersteller Altera Corporation
Logo Altera Corporation Logo 




Gesamt 30 Seiten
EPM7128B Datasheet, Funktion
www.DataSheet4U.com
September 2003, ver. 3.4
®
MAX 7000B
Programmable Logic
Device
Data Sheet
Features...
f
High-performance 2.5-V CMOS EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX®) architecture (see Table 1)
– Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V
MAX 7000A device families
– High-density PLDs ranging from 600 to 10,000 usable gates
– 3.5-ns pin-to-pin logic delays with counter frequencies in excess
of 303.0 MHz
Advanced 2.5-V in-system programmability (ISP)
– Programs through the built-in IEEE Std. 1149.1 Joint Test Action
Group (JTAG) interface with advanced pin-locking capability
– Enhanced ISP algorithm for faster programming
– ISP_Done bit to ensure complete programming
– Pull-up resistor on I/O pins during in-system programming
– ISP circuitry compliant with IEEE Std. 1532
For information on in-system programmable 5.0-V MAX 7000S or 3.3-V
MAX 7000A devices, see the MAX 7000 Programmable Logic Device Family
Data Sheet or the MAX 7000A Programmable Logic Device Family Data Sheet.
Table 1. MAX 7000B Device Features
Feature
Usable gates
Macrocells
Logic array blocks
Maximum user I/O
pins
tPD (ns)
tSU (ns)
tFSU (ns)
tCO1 (ns)
fCNT (MHz)
EPM7032B
600
32
2
36
3.5
2.1
1.0
2.4
303.0
EPM7064B
1,250
64
4
68
3.5
2.1
1.0
2.4
303.0
EPM7128B
2,500
128
8
100
4.0
2.5
1.0
2.8
243.9
EPM7256B
5,000
256
16
164
5.0
3.3
1.0
3.3
188.7
EPM7512B
10,000
512
32
212
5.5
3.6
1.0
3.7
163.9
Altera Corporation
DS-MAX7000B-3.4
1






EPM7128B Datasheet, Funktion
MAX 7000B Programmable Logic Device Data Sheet
Figure 1. MAX 7000B Device Block Diagram
INPUT/GCLK1
INPUT/OE2/GCLK2
INPUT/OE1
INPUT/GCLRn
6 or 10 Output Enables (1)
2 to 16 I/O
2 to 16 LAB A
I/O 2 to 16
Control
Block
Macrocells
1 to 16
36
16
6 or 10 Output Enables (1)
LAB B 2 to 16
36 Macrocells
17 to 32
16
2 to 16 I/O
Control
Block
2 to 16 I/O
2 to 16 I/O
6 or 10
2 to 16 LAB C
2 to 16
PIA
2 to 16
LAB D 2 to 16
6 or 10
I/O 2 to 16
Control
Block
Macrocells
33 to 48
36
16
36 Macrocells
49 to 64
16
2 to 16 I/O
Control
Block
2 to 16 I/O
6 or 10
2 to 16
2 to 16
6 or 10
Note:
(1) EPM7032B, EPM7064B, EPM7128B, and EPM7256B devices have six output enables. EPM7512B devices have ten
output enables.
Logic Array Blocks
The MAX 7000B device architecture is based on the linking of
high-performance LABs. LABs consist of 16 macrocell arrays, as shown in
Figure 1. Multiple LABs are linked together via the PIA, a global bus that
is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
Direct input paths from I/O pins to the registers that are used for fast
setup times
6 Altera Corporation

6 Page









EPM7128B pdf, datenblatt
MAX 7000B Programmable Logic Device Data Sheet
Figure 5. MAX 7000B PIA Routing
To LAB
PIA Signals
While the routing delays of channel-based routing schemes in masked or
field-programmable gate arrays (FPGAs) are cumulative, variable, and
path-dependent, the MAX 7000B PIA has a predictable delay. The PIA
makes a design’s timing performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or VCC. Figure 6 shows the I/O
control block for MAX 7000B devices. The I/O control block has
six or ten global output enable signals that are driven by the true or
complement of two output enable signals, a subset of the I/O pins, or a
subset of the I/O macrocells.
12 Altera Corporation

12 Page





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