PDF EDI9LC644V Data sheet ( Hoja de datos )

Número de pieza	EDI9LC644V
Descripción	128Kx32 SSRAM/1Mx32 SDRAM
Fabricantes	WEDC
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No Preview Available ! www.DataSheet4U.com EDI9LC644V 128Kx32 SSRAM/1Mx32 SDRAM EXTERNAL MEMORY SOLUTION FOR TEXAS INSTRUMENTS TMS320C6000 DSP FEATURES n Clock speeds: • SSRAM: 200, 166,150, and 133 MHz • SDRAMs: 125 and 100 MHz n DSP Memory Solution • Texas Instruments TMS320C6201 • Texas Instruments TMS320C6701 n Packaging: • 153 pin BGA, JEDEC MO-163 n 3.3V Operating supply voltage n Direct control interface to both the SSRAM and SDRAM ports on the “C6x” n Common address and databus n 65% space savings vs. monolithic solution n Reduced system inductance and capacitance FIG. 1 PIN CONFIGURATION DESCRIPTION The EDI9LC644VxxBC is a 3.3V, 128K x 32 Synchronous Pipeline SRAM and a 1Mx32 Synchronous DRAM array con- structed with one 128K x 32 SBSRAM and two 1Mx16 SDRAM die mounted on a multilayer laminate substrate. The device is packaged in a 153 lead, 14mm by 22mm, BGA. The EDI9LC644VxxBC provides a total memory solution for the Texas Instr uments TMS320C6201 and the TMS320C6701 DSPs The Synchronous Pipeline SRAM is available with clock speeds of 200, 166,150, and 133 MHz, allowing the user to develop a fast external memory for the SSRAM inter- face port . The SDRAM is available in clock speeds of 125 and 100 MHz, allowing the user to develop a fast external memory for the SDRAM interface port . BOTTOM VIEW 12 3456 A DQ19 DQ23 VCC VSS VSS VSS B DQ18 DQ22 VCC VSS SDCE VSS C VCCQ VCCQ VCC SDWE SDA10 NC D DQ17 DQ21 VCC VSS VSS VSS E DQ16 DQ20 VCC VSS SDCLK VSS F VCCQ VCCQ VCC VSS VSS VSS G NC NC NC SDRAS SDCAS VSS H NC NC A8 VSS VSS NC J A6 A7 A9 VSS VSS NC K NC/A17 NC/A18 NC/A19 VSS VSS NC L NC NC NC BWE2 BWE3 NC M VCCQ VCCQ VCC BWE0 BWE1 NC N DQ12 DQ11 VCC VSS VSS VSS P DQ13 DQ10 VCC VSS SSCLK VSS R VCCQ VCCQ VCC VSS VSS VSS T DQ14 DQ9 VCC SSADC SSWE NC U DQ15 DQ8 VCC SSOE SSCE NC 12 3456 789 VCC DQ24 DQ28 A VCC DQ25 DQ29 B VCC VCCQ VCCQ C VCC DQ26 DQ30 D VCC DQ27 DQ31 E VCC VCCQ VCCQ F A2 A4 A5 G A1 A3 A10 H A0 A11 A12 J NC A13 A14 K NC A15 A16 L VCC VCCQ VCCQ M VCC DQ4 DQ0 N VCC DQ5 DQ1 P VCC VCCQ VCCQ R VCC DQ6 DQ2 T VCC DQ7 DQ3 U 789 A0-16 DQ0-31 SSCLK SSADC SSWE SSOE SDCLK SDRAS SDCAS SDWE SDA10 BWE0-3 SSCE SDCE VCC VCCQ VSS NC PIN DESCRIPTION Address Bus Data Bus SSRAM Clock SSRAM Address Status Control SSRAM Write Enable SSRAM Output Enable SDRAM Clock SDRAM Row Address Strobe SDRAM Column Address Strobe SDRAM Write Enable SDRAM Address 10/auto precharge SSRAM Byte Write Enables SDRAM SDQM 0 - 3 Chip Enable SSRAM Device Chip Enable SDRAM Device Power Supply pins, 3.3V Data Bus Power Supply pins, 3.3V (2.5V future) Ground No Connect January 2002 Rev. 4 ECO# 14667 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 1 page EDI9LC644V SSRAM AC CHARACTERISTICS (EDI9LC644V) Parameter Clock Cycle Time Clock HIGH Time Clock LOW Time Clock to output valid Clock to output invalid Clock to output on Low-Z Clock to output in High-Z Output Enable to output valid Output Enable to output in Low-Z Output Enable to output in High-Z Address, Control, Data-in Setup Time to Clock Address, Control, Data-in Hold Time to Clock Symbol tKHKH tKLKH tKHKL tKHQV tKHQX tKQLZ tKQHZ tOELQV tOELZ tOEHZ tS tH 200MHz Min Max 5 1.6 1.6 2.5 1.5 0 1.5 3 2.5 0 3.0 1.5 0.5 166MHz Min Max 6 2.4 2.4 3.5 1.5 0 1.5 3.5 3.5 0 3.5 1.5 0.5 150MHz Min Max 7 2.6 2.6 3.8 1.5 0 1.5 3.8 3.8 0 3.5 1.5 0.5 133MHz Min Max 8 2.8 2.8 4.0 1.5 0 1.5 4.0 4.0 0 3.8 1.5 0.5 Units ns ns ns ns ns ns ns ns ns ns ns ns Operation Deselected Cycle, Power Down WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst SSRAM OPERATION TRUTH TABLE Address Used None External External External Current Current Current Current Current Current SSCE H L L L X X H H X H SSADS L L L L H H H H H H SSWE X L H H H H H H L L SSOE X X L H L H L H X X DQ High-Z D Q High-Z Q High-Z Q High-Z D D Note: 1. X means “don’t care”, H means logic HIGH. L means logic LOW. 2. All inputs except SSOE must meet setup and hold times around the rising edge (LOW to HIGH) of SSCLK. 3. Suspending burst generates wait cycle 4. For a write operation following a read operation, SSOE must be HIGH before the input data required setup time plus High-Z time for SSOE and staying HIGH though out the input data hold time. 5. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. SSRAM PARTIAL TRUTH TABLE Function READ WRITE one Byte (DQ0-7) WRITE all Bytes SSWE H L L BWE0 X L L BWE1 BWE2 XX HH LL BWE3 X H L 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 5 Page EDI9LC644V SDRAM CURRENT STATE TRUTH TABLE (CONT.) Current State Refreshing Mode Register Accessing SDCE SDRAS SDCAS LL LL LL LL LH LH LH LH HX LL LL LL LL LH LH LH LH HX L L H H L L H H X L L H H L L H H X Command SDWE L A11 SDA 10-A 0 (BA) OP Code Description Mode Register Set Action ILLEGAL HX X Auto or Self Refresh ILLEGAL LX X Precharge ILLEGAL H BA Row Address Bank Activate ILLEGAL L BA Column Write ILLEGAL H BA Column Read ILLEGAL LX X Burst Termination No Operation; Idle after tRC HX X No Operation No Operation; Idle after tRC XX X Device Deselect No Operation; Idle after tRC L OP Code Mode Register Set ILLEGAL HX X Auto or Self Refresh ILLEGAL LX X Precharge ILLEGAL H BA Row Address Bank Activate ILLEGAL L BA Column Write ILLEGAL H BA Column Read ILLEGAL LX X Burst Termination ILLEGAL H X X No Operation No Operation; Idle after two clock cycles XX X Device Deselect No Operation; Idle after two clock cycles Notes NOTES: 1. Both Banks must be idle otherwise it is an illegal action. 2. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 3. The minimum and maximum Active time (tRAS) must be satisfied. 4. The RAS to CAS Delay (tRCD) must occur before the command is given. 5. Address SDA10 is used to determine if the Auto Precharge function is activated. 6. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. 11 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 11 Page

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