|
|
PDF AD7610 Data sheet ( Hoja de datos )
| Número de pieza | AD7610 | |
| Descripción | Unipolar/Bipolar Programmable Input PulSAR ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD7610 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
16-Bit, 250 kSPS, Unipolar/Bipolar
Programmable Input PulSAR® ADC
AD7610
FEATURES
Multiple pins/software programmable input ranges:
5 V, 10 V, ±5 V, ±10 V
Pins or serial SPI®-compatible input ranges/mode selection
Throughput: 250 kSPS
16-bit resolution with no missing codes
INL: ±0.75 LSB typ, ±1.5 LSB max (±23 ppm of FSR)
SNR: 94 dB @ 2 kHz
iCMOS® process technology
5 V internal reference: typical drift 3 ppm/°C;
On-chip temperature sensor
No pipeline delay (SAR architecture)
Parallel (16- or 8-bit bus) and serial 5 V/3.3 V interface
SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
Power dissipation
90 mW @ 250 kSPS
10 mW @ 1 kSPS
48-lead LQFP and LFCSP (7 mm × 7 mm) packages
APPLICATIONS
Process control
Medical instruments
High speed data acquisition
Digital signal processing
Instrumentation
Spectrum analysis
ATE
FUNCTIONAL BLOCK DIAGRAM
TEMP REFBUFIN REF REFGND VCC VEE DVDD DGND
AGND
AVDD
PDREF
PDBUF
IN+
IN–
REF
REF
AMP
SWITCHED
CAP DAC
CNVST
PD
RESET
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
AD7610
SERIAL
DATAPORT
SERIAL
CONFIGURATION
PORT
16
PARALLEL
INTERFACE
OVDD
OGND
D[15:0]
SER/PAR
BYTESWAP
OB/2C
BUSY
RD
CS
BIPOLAR TEN
Figure 1.
GENERAL DESCRIPTION
The AD7610 is a 16-bit charge redistribution successive approxi-
mation register (SAR), architecture analog-to-digital converter
(ADC) fabricated on Analog Devices, Inc.’s iCMOS high voltage
process. The device is configured through hardware or via a
dedicated write only serial configuration port for input range
and operating mode. The AD7610 contains a high speed 16-bit
sampling ADC, an internal conversion clock, an internal reference
(and buffer), error correction circuits, and both serial and parallel
system interface ports. A falling edge on CNVST samples the
analog input on IN+ with respect to a ground sense, IN−. The
AD7610 features four different analog input ranges: 0 V to 5 V, 0 V
to 10 V, ±5 V, and ±10 V. Power consumption is scaled linearly
with throughput. The device is available in Pb-free 48-lead, low-
profile quad flat package (LQFP) and a lead frame chip-scale
(LFCSP_VQ) package. Operation is specified from −40°C to
+85°C.
Table 1. 48-Lead 14-/16-/18-Bit PulSAR Selection
Type
100 kSPS to 500 kSPS to 800 kSPS to
250 kSPS
570 kSPS
1000 kSPS
Pseudo
Differential
AD7651
AD7660
AD7661
AD7650
AD7652
AD7664
AD7666
AD7653
AD7667
True Bipolar
AD7610
AD7663
AD7665
AD7612
AD7671
AD7951
True
Differential
AD7675
AD7676
AD7677
18-Bit, True
Differential
Multichannel/
Simultaneous
AD7678
AD7679
AD7654
AD7655
AD7674
>1000
kSPS
AD7621
AD7622
AD7623
AD7641
AD7643
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
AD7610
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
CONVERSION AND RESET (See Figure 33 and Figure 34)
Convert Pulse Width
Time Between Conversions
CNVST Low to BUSY High Delay
BUSY High (Except Master Serial Read After Convert)
Aperture Delay
End of Conversion to BUSY Low Delay
Conversion Time
Acquisition Time
RESET Pulse Width
PARALLEL INTERFACE MODES (See Figure 35 and Figure 37)
CNVST Low to DATA Valid Delay
DATA Valid to BUSY Low Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
MASTER SERIAL INTERFACE MODES1 (See Figure 39 and Figure 40)
CS Low to SYNC Valid Delay
CS Low to Internal SDCLK Valid Delay1
CS Low to SDOUT Delay
CNVST Low to SYNC Delay, Read During Convert
SYNC Asserted to SDCLK First Edge Delay
Internal SDCLK Period2
Internal SDCLK High2
Internal SDCLK Low2
SDOUT Valid Setup Time2
SDOUT Valid Hold Time2
SDCLK Last Edge to SYNC Delay2
CS High to SYNC HI-Z
CS High to Internal SDCLK HI-Z
CS High to SDOUT HI-Z
BUSY High in Master Serial Read After Convert2
CNVST Low to SYNC Delay, Read After Convert
SYNC Deasserted to BUSY Low Delay
SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES1 (See Figure 42,
Figure 43, and Figure 45)
External SDCLK, SCCLK Setup Time
External SDCLK Active Edge to SDOUT Delay
SDIN/SCIN Setup Time
SDIN/SCIN Hold Time
External SDCLK/SCCLK Period
External SDCLK/SCCLK High
External SDCLK/SCCLK Low
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
t32
t33
t34
t35
t36
t37
Min
10
4
10
380
10
20
2
3
30
15
10
4
5
5
5
2
5
5
25
10
10
Typ Max
35
1.45
2
1.45
1.41
40
15
10
10
10
560
45
See Table 4
1.31
25
10
10
10
18
Unit
ns
μs
ns
μs
ns
ns
μs
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
1 In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2 In serial master read during convert mode. See Table 4 for serial mode read after convert mode.
Rev. 0 | Page 5 of 32
5 Page 
AD7610
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = DVDD = 5 V; OVDD = 5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; TA = 25°C.
1.5 1.5
1.0 1.0
0.5 0.5
00
–0.5 –0.5
–1.0 –1.0
–1.5
0
250
200
16384
32768
CODE
49152
Figure 5. Integral Nonlinearity vs. Code
65536
NEGATIVE INL
POSITIVE INL
150
100
50
0
–1.0 –0.8 –0.6 –0.4 –0.2 0
0.2 0.4 0.6 0.8 1.0
INL DISTRIBUTION (LSB)
Figure 6. Integral Nonlinearity Distribution (296 Devices)
250000
200000
211404
σ = 0.44
150000
100000
50000
27510
22202
00
7FFF
0
8000
4
8001
8002 8003
CODE IN HEX
8004
0
8005
0
8006
Figure 7. Histogram of 261,120 Conversions of a DC Input
at the Code Center
–1.5
0
16384
32768
CODE
49152
65536
Figure 8. Differential Nonlinearity vs. Code
180
NEGATIVE DNL
160 POSITIVE DNL
140
120
100
80
60
40
20
0
–1.0 –0.8 –0.6 –0.4 –0.2 0
0.2 0.4 0.6 0.8 1.0
DNL DISTRIBUTION (LSB)
Figure 9. Differential Nonlinearity Distribution (296 Devices)
140000
120000
132700
127179
σ = 0.51
100000
80000
60000
40000
20000
0
0
8000
0
8001
1072
8002
8003 8004
CODE IN HEX
169
8005
0
8006
0
8007
Figure 10. Histogram of 261,120 Conversions of a DC Input
at the Code Transition
Rev. 0 | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD7610.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD7610 | Unipolar/Bipolar Programmable Input PulSAR ADC | Analog Devices |
| AD7612 | 16-bit charge redistribution successive approximation register | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |