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ADN2891 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADN2891
Beschreibung Amplifier
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
ADN2891 Datasheet, Funktion
www.DataSheet4U.com
FEATURES
Input sensitivity: 4 mV p-p
80 ps rise/fall times
CML outputs: 700 mV p-p differential
Programmable LOS detector: 3.5 mV to 35 mV
Rx signal strength indicator (RSSI)
SFF-8472-compliant average power measurement
Single-supply operation: 3.3 V
Low power dissipation: 145 mW
Available in space-saving 3 mm × 3 mm, 16-lead LFCSP
Extended temperature range: −40°C to +95°C
SFP reference design available
APPLICATIONS
SFP/SFF/GBIC optical transceivers
OC-3/OC-12/OC-48, GbE, Fibre Channel (FC) receivers
10GBASE-LX4 transceivers
WDM transponders
3.3 V, 3.2 Gbps,
Limiting Amplifier
ADN2891
GENERAL DESCRIPTION
The ADN2891 is a 3.2 Gbps limiting amplifier with integrated
loss-of-signal (LOS) detection circuitry and a received signal
strength indicator (RSSI). This part is optimized for SONET,
Gigabit Ethernet (GbE), and Fibre Channel optoelectronic
conversion applications. The ADN2891 has a differential input
sensitivity of 4 mV p-p and accepts up to a 2.0 V p-p differential
input overload voltage. The ADN2891 supports current mode
logic (CML) outputs with controlled rise and fall times.
By monitoring the bias current through a photodiode, the on-
chip RSSI detector measures the average power received with
2% typical linearity over the entire valid input range of the
photodiode. The on-chip RSSI detector facilitates SFF-8472-
compliant optical transceivers by eliminating the need for
external RSSI detector circuitry.
Additional features include a programmable loss-of-signal
(LOS) detector and output squelch.
The ADN2891 is available in a 3 mm × 3 mm, 16-lead LFCSP.
FUNCTIONAL BLOCK DIAGRAM
AVCC AVEE
DRVCC DRVEE
ADN2891
ADN2880
PIN
NIN
DRVCC
50Ω 50Ω
OUTP
OUTN
50Ω
PD_VCC
PD_CATHODE
50Ω
3kΩ
VREF
RSSI/LOS
DETECTOR
+V
10kΩ
LOS
RSSI_OUT ADuC7020
CAZ1
CAZ2
0.01μF
THRADJ SQUELCH
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2005 Analog Devices, Inc. All rights reserved.






ADN2891 Datasheet, Funktion
ADN2891
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
16 15 14 13
AVCC 1
12 DRVCC
PIN 2 ADN2891 11 OUTP
NIN
3
TOP VIEW
(Not to Scale)
10
OUTN
AVEE 4
9 DRVEE
5678
Figure 2. Pin Configuration
Note that the LFCSP has an exposed pad on the bottom. To improve heat dissipation, the exposed pad must be soldered to the GND plane
with filled vias.
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
I/O Type1
1 AVCC
P
2 PIN
AI
3 NIN
AI
4 AVEE
P
5 THRADJ AO
6 CAZ1
AI
7 CAZ2
AI
8
9
10
11
12
13
14
15
16
Exposed
Pad
LOS
DRVEE
OUTN
OUTP
DRVCC
SQUELCH
RSSI_OUT
PD_VCC
PD_CATHODE
Pad
DO
P
DO
DO
P
DI
AO
P
AO
P
Descriptions
Analog Power Supply.
Differential Data Input, Positive Port, 50 Ω On-Chip Termination.
Differential Data Input, Negative Port, 50 Ω On-Chip Termination.
Analog Ground.
LOS Threshold Adjust Resistor.
If needed, one capacitor can connect between the CAZ1 and CAZ2 pin for
input offset correction.
If needed, one capacitor can connect between the CAZ1 and CAZ2 pin for
input offset correction.
LOS Detector Output, Open Collector.
Output Buffer Ground.
Differential Data Output, CML, Negative Port, 50 Ω On-Chip Termination.
Differential Data Output, CML, Positive Port, 50 Ω On-Chip Termination.
Output Buffer Power Supply.
Disable Outputs, 100 kΩ On-Chip Pull-Down Resistor.
Average Current Output.
Power Input for RSSI Measurement.
Photodiode Bias Voltage.
Connect to Ground.
1 P = power; DI = digital input; DO = digital output; AI = analog input; and AO = analog output.
Rev. A | Page 6 of 16

6 Page









ADN2891 pdf, datenblatt
ADN2891
PCB Layout
Figure 21 shows the recommended PCB layout. The 50 Ω
transmission lines are the traces that bring the high frequency
input and output signals (PIN, NIN, OUTP, and OUTN) to the
SMA connectors with minimum reflection. To avoid a signal
skew between the differential traces, each differential PIN/NIN
and OUTP/OUTN pair should have matched trace lengths from
the signal pins to the corresponding SMA connectors. C1, C2,
C3, and C4 are ac coupling capacitors in series with the high
speed, signal input/output paths. To minimize the possible
mismatch, the ac coupling capacitor pads should be the same
width as the 50 Ω transmission line trace width. To reduce
supply noise, a 1 nF decoupling capacitor should be placed on
the same layer as close as possible to the VCC pins. A 0.1 μF
decoupling capacitor can be placed on the bottom of the PCB
directly underneath the 1 nF capacitor. All high speed, CML
outputs have internal 50 Ω resistor termination between the
output pin and VCC. The high speed inputs, PIN and NIN, also
have the internal 50 Ω termination to an internal reference
voltage.
As with any high speed, mixed-signal design, keep all high
speed digital traces away from sensitive analog nodes.
Soldering Guidelines for the LFCSP
The lands on the 16-lead LFCSP are rectangular. The PCB pad
for these should be 0.1 mm longer than the package land length
and 0.05 mm wider than the package land width. The land
should be centered on the pad. This ensures that the solder joint
size is maximized. The bottom of the LFCSP has a central
exposed pad. The pad on the printed circuit board should be at
least as large as the exposed pad. Users must connect the
exposed pad to VEE using filled vias so that solder does not
leak through the vias during reflow. This ensures a solid
connection from the exposed pad to VEE.
TO ROSA
PLACE C5 ON
BOTTOM OF BOARD
UNDERNEATH C6
C1
PIN
4mm
NIN
C2
C6
R1, C9, C10 ON BOTTOM
1 EXPOSED PAD
VIAS TO
GND
DOUBLE-VIAS TO REDUCE
INDUCTANCE TO SUPPLY
AND GND
PLACE C7 ON
BOTTOM OF BOARD
UNDERNEATH C8
C8 C3
OUTP
OUTN
C4
VIA TO C12, R2
ON BOTTOM
DOUBLE-VIA TO GND
TO REDUCE INDUCTANCE
C11 VIA TO BOTTOM
Figure 21. Recommended PCB Layout (Top View)
Rev. A | Page 12 of 16

12 Page





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