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AD8386 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD8386
Beschreibung 12-Channel Output Decimating LCD Driver
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD8386 Datasheet, Funktion
www.DataSheet4U.com
FEATURES
High voltage drive
To within 1.3 V of supply rails
Output short-circuit protection
High update rates
Fast, 100 Ms/s 10-bit input data update rate
Static power dissipation: 1.4 W
Voltage-controlled video reference (brightness), offset,
and full-scale (contrast) output levels
INV bit reverses polarity of video signal
3.3 V logic, 9 V to 18 V analog supplies
High accuracy voltage outputs
Laser trimming eliminates the need for adjustments or
calibration
Flexible logic
XFR allows parallel AD8386 operation
Fast settling into capacitive loads
35 ns settling time to 0.25% into 150 pF load
Slew rate 400 V/μs
Available in 64-lead 9 mm × 9 mm LFCSP_VQ
GENERAL DESCRIPTION
The AD8386 provides a fast, 10-bit, latched, decimating digital
input that drives 12 high voltage outputs. Input words with
10 bits are loaded sequentially into 12 separate high speed,
bipolar DACs. Flexible digital input format allows several
AD8386s to be used in parallel in high resolution displays.
The output signal can be adjusted for dc reference, signal
inversion, and contrast for maximum flexibility.
The AD8386 is fabricated on ADI’s fast bipolar, 26 V XFHV
process, which provides fast input logic, bipolar DACs with
trimmed accuracy and fast settling, high voltage, precision
drive amplifiers on the same chip.
The AD8386 dissipates 1.4 W nominal static power.
The AD8386 is offered in a 64-lead 9 mm × 9 mm LFCSP_VQ
package and operates over the commercial temperature range of
0°C to 85°C.
10-Bit, 12-Channel Output
Decimating LCD Driver
AD8386
FUNCTIONAL BLOCK DIAGRAM
BYP
VRH
VRH
VRL
DB(0:9)
2
10
R/L
CLK
XFR
3
INV
GCTL
GSW
TSW
SDI
SCL
SEN
SVRH
SVRL
SVRL
3
3
2
BIAS
SCALING
CONTROL
TWO-STAGE 10-BIT
LATCH
DACs
SEQUENCE
CONTROL
INV
CONTROL
12-BIT
SHIFT
REGISTER
8-BIT
DAC
Figure 1.
VID0
VID1
VID2
VID3
VID4
12 VID5
VID6
VID7
VID8
VID9
VID10
VID11
VAO
AD8386
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.






AD8386 Datasheet, Funktion
AD8386
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
AVCCx − AGNDx
DVCC − DGND
Input Voltage
Maximum Digital Input Voltage
Minimum Digital Input Voltage
Maximum Analog Input Voltage
Minimum Analog Input Voltage
Internal Power Dissipation1
LFCSP @ TA = 25°C
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range
(Soldering 10 sec)
Rating
18 V
4.5 V
DVCC + 0.5 V
DGND − 0.5 V
AVCC + 0.5 V
AGND − 0.5 V
3.7 W
0°C to 85°C
–65°C to +125°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1 64-lead VQ_LFCSP:
θJA = 27°C/W in still air (JEDEC STD, 4-layer PCB with 16 vias on Epad)
θJA = 25°C/W @ 200 lfm airflow (JEDEC STD, 4-layer PCB with 16 vias on Epad)
θJA = 24°C/W @ 400 lfm airflow (JEDEC STD, 4-layer PCB with 16 vias on Epad)
ΨJT = 0.2°C/W in still air (JEDEC STD, 4-layer PCB with 16 vias on Epad)
ΨJB = 13.8°C/W in still air (JEDEC STD, 4-layer PCB with 16 vias on Epad)
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8386 is limited by its junction temperature. The maximum
safe junction temperature for plastic encapsulated devices, as
determined by the glass transition temperature of the plastic, is
approximately 150°C. Exceeding this limit temporarily may
cause a shift in the parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can
result in device failure.
OVERLOAD PROTECTION
The AD8386 overload protection circuit consists of an output
current limiter and a thermal protection circuit.
When TSW is LOW, the thermal protection circuit is disabled,
and the output current limiter is turned on. The maximum
current at any one output of the AD8386 is internally limited to
100 mA average. In the event of a momentary short circuit
between a video output and a power supply rail (AVCC or
AGND), the output current limit is sufficiently low to provide
temporary protection.
When TSW is HIGH, the output current limiter, as well as the
thermal protection circuit, is turned on. The thermal protection
circuit debiases the output amplifier when the junction
temperature reaches the internally set trip point. In the event of
an extended short circuit between a video output and a power
supply rail, the output amplifier current continues to switch
between 0 mA and 100 mA typical with a period determined by
the thermal time constant and the hysteresis of the thermal trip
point. The thermal protection circuit limits the average junction
temperature to a safe level, which provides long-term
protection.
EXPOSED PADDLE
To ensure optimal thermal performance, the exposed paddle
must be electrically connected to an external plane, such as
AVCC or GND, as described in the Applications section.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 20

6 Page









AD8386 pdf, datenblatt
AD8386
SERIAL INTERFACE BLOCK DIAGRAM AND TIMING
SVRH
SVRL
SDI
SCL
SEN
12-BIT SHIFT REGISTER
SDICODE
8
SDICODE
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11
VAO = SVRL + SDICODE × (SVRH – SVRL)/256
SDAC
SELECT LOAD
VAO
75kΩ
CONTROL
TSW
10kΩ
VIDEO
DACs
THERMAL
SWITCH
12
12
12
VID(0:11)
GSW
GCTL
Figure 7. Serial Interface Block Diagram
SEN
SCL
SDI D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VAO
Figure 8. Serial Interface Timing Diagram
SEN
SCL
SDI
t20 t21 t22
t24 t25
D11
D10
D1
t23
D0
VAO
t26
Figure 9. Serial Interface Timing Diagram
Table 6.
Parameter
SEN to SCL Setup Time, t20
SCL, High Level Pulse Width, t21
SCL, Low Level Pulse Width, t22
SCL to SEN Hold Time, t23
SDI Setup Time, t24
SDI Hold Time, t25
VAO Settling Time, t26
VAO Settling Time, t26
Conditions
SVFS = 5 V, to 0.5 %, CL = 100 pF
SVFS = 5 V, to 0.5 %, CL = 33 μF
Min Typ Max Unit
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
12
μs
15 ms
Rev. 0 | Page 12 of 20

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