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Teilenummer | A64S16161 |
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Beschreibung | 2M X 16 Bit Low Voltage Super RAM | |
Hersteller | AMIC Technology | |
Logo | ||
Gesamt 16 Seiten Preliminary
A64S16161
2M X 16 Bit Low Voltage Super RAM
Features
● Memory Cell : Dynamic memory( DRAM )
● Refresh: Completely free
● Power Down: Control by CS2( No Data Retention )
● Byte Control : Capable of single byte operation
● Power Consumption: 100μA( Standby Current )
● Operating Temperature Range: -40’C~+85’C
● Composition:2,097,152 Word X 16 Bit
● Supply Power Voltage:2.70V to 3.30V
● Access Time: 70nS
● Access Time ( Page Access Read ): 30nS
● I/O Terminal :Input / Output Common 3-state output
Pin Description
Pin Name Description
CS1#
Chip select 1 ( Low Active )
CS2
Chip select 2 ( High Active )
WE#
Write enable ( Low Active )
OE#
Output enable ( Low Active )
A0 to A20
Address Input ( A0 to A2 : Page Address)
IO0-7
Lower Byte Input / Output
IO8-15
Upper Byte Input / Output
LB# Lower Byte Control ( Low Active )
UB#
Upper Byte Control ( Low Active )
VCC
Power Supply
VSS
Ground ( 0V)
A
B
C
D
E
F
G
H
123456
LB# OE# A0 A1 A2 CE2
DQ8 UB# A3
A4
CE1#
DQ0
DQ9 DQ10 A5
A6 DQ1 DQ2
VSS DQ11 A17 A7
DQ3 VCC
VCC DQ12 NC
A16 DQ4 VSS
DQ14 DQ13 A14 A15 DQ5 DQ6
DQ15 A19 A12 A13 WE# DQ7
A18 A8 A9 A10 A11 A20
Description
A64S16161 is a virtually static RAM, which uses DRAM type memory cells, but it has refresh transparency, so that you need
not to imply refresh operation. Furthermore the interface is completely compatible to a low power Asynchronous type SRAM, you
can operate as same as the Asynchronous SRAM.
A64S16161 is a 2,097,152 Words X 16 bit asynchronous random access memory on a monolithic CMOS chip with
marvelous low power consumption technology. Its low power and also low noise makes it ideal for mobile applications.
PRELIMINARY (December, 2003, Version 0.0)
1
AMIC Technology Corp.
AC Electrical Characteristics
Read Cycle (Ta = - 30 ~ 85’C)
Parameter
Symbol
Read cycle time
tRC
Page read cycle time
Address access time
Page address access time
CS1 # access time
OE # access time
LB # , UB # access time
CS1# high pulse width
Address set up to OE L #
CS1 # output set time
CS1 # output floating time
LB # , UB # output set time
LB # , UB # output floating time
OE # output set time
OE # output floating time
Output hold time
tRCP
tACC
tACCP
tACS
tOE
tAB
tC1H
tASO
tCHZ
tCLZ
tBLZ
tBLZ
tOLZ
tOHZ
tOH
Teat Conditions
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
1
Min
70
30
-
-
-
-
-
30
-5
0
-
0
-
0
-
5
A64S16161
Max
32000
32000
70
30
70
35
25
-
-
-
15
-
15
-
15
-
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Write Cycle (Ta= - 40~85’C)
Parameter
Write cycle time
Chip select time
CS1# H pulse width
Address enable time
Address set up time
Write pulse width
LB,UB select time
Address hold time
Data set up time
Data hold time
Symbol
tWC
tCW
tC1H
tAW
tAS
tWP
tBW
tWR
tDW
tDH
Test Conditions
1
1
1
1
1
1
1
1
1
Min
70
60
30
60
0
40
60
0
30
0
Max
32000
-
-
-
-
-
-
-
-
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS
PRELIMINARY (December, 2003, Version 0.0)
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AMIC Technology Corp.
6 Page Power Down Mode Entry / Exit
CS1#
CS2
tSSP
tC2LP
A64S16161
tSHP
tHPD
Power Up
CS1#
CS2
tSHU
tHPU
VCC
VCC(min)
Data Retention(1)
Address
(A20-A3)
CS1#
tBAH
This applies for both read and write.
PRELIMINARY (December, 2003, Version 0.0)
12
AMIC Technology Corp.
12 Page | ||
Seiten | Gesamt 16 Seiten | |
PDF Download | [ A64S16161 Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
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