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A67P93361 Schematic ( PDF Datasheet ) - AMIC Technology

Teilenummer A67P93361
Beschreibung (A67P06181 / A67P93361) Flow-through ZeBL SRAM
Hersteller AMIC Technology
Logo AMIC Technology Logo 




Gesamt 18 Seiten
A67P93361 Datasheet, Funktion
www.DataSheet4U.com
Preliminary
A67P06181/A67P93361 Series
1M X 18, 512K X 36 LVTTL, Flow-through ZeBLTM SRAM
Document Title
1M X 18, 512K X 36 LVTTL, Flow-through ZeBLTM SRAM
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
September, 20, 2004
Remark
Preliminary
PRELIMINARY (September, 2004, Version 0.0)
AMIC Technology, Corp.






A67P93361 Datasheet, Funktion
Pin Description
Pin No.
LQFP (X18)
LQFP (X36)
37
36
35,34,33,32,
100,99,82,81
44,45,46,47,
48,49,50,83
84
80
93 (BW1)
94 (BW2 )
37
36
35,34,33,32,
100,99,82,81
45,46,47,48,
49,50,83,84
44
93 (BW1)
94 (BW2 )
95 (BW3 )
96 (BW4 )
89 89
98 98
92 92
97 97
86 86
85 85
87 87
A67P06181/A67P93361 Series
Symbol
Description
A0
A1
A2 – A9
A11-A18
A19
A10
BW1
BW2
BW3
BW4
CLK
CE
CE2
CE2
OE
ADV/ LD
CEN
Synchronous Address Inputs : These inputs are registered
and must meet the setup and hold times around the rising
edge of CLK. Pins 83 and 84 are reserved as address bits
for higher-density 9Mb and 18Mb DBA SRAMs, respectively.
A0 and A1 are the two lest significant bits (LSB) of the
address field and set the internal burst counter if burst is
desired.
Synchronous Byte Write Enables : These active low inputs
allow individual bytes to be written when a WRITE cycle is
active and must meet the setup and hold times around the
rising edge of CLK. BYTE WRITEs need to be asserted on
the same cycle as the address, BWs are associated with
addresses and apply to subsequent data. BW1 controls I/Oa
pins; BW2 controls I/Ob pins; BW3 controls I/Oc pins;
BW4 controls I/Od pins.
Clock : This signal registers the address, data, chip enables,
byte write enables and burst control inputs on its rising edge.
All synchronous inputs must meet setup and hold times
around the clock’s rising edge.
Synchronous Chip Enable : This active low input is used to
enable the device. This input is sampled only when a new
external address is loaded (ADV/LD LOW).
Synchronous Chip Enable : This active low input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/LD LOW). This input can be used
for memory depth expansion.
Synchronous Chip Enable : This active high input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/LD LOW). This input can be used
for memory depth expansion.
Output Enable : This active low asynchronous input enables
the data I/O output drivers.
Synchronous Address Advance/Load : When HIGH, this
input is used to advance the internal burst counter,
controlling burst access after the external address is loaded.
When HIGH, R/ W is ignored. A LOW on this pin permits a
new address to be loaded at CLK rising edge.
Synchronous Clock Enable : This active low input permits
CLK to propagate throughout the device. When HIGH, the
device ignores the CLK input and effectively internally
extends the previous CLK cycle. This input must meet setup
and hold times around the rising edge of CLK.
PRELIMINARY (September, 2004, Version 0.0)
6
AMIC Technology, Corp.

6 Page









A67P93361 pdf, datenblatt
A67P06181/A67P93361 Series
AC Characteristics (Note 4)
(0°C TA 70°C, VCC = +2.5V± 5%)
Symbol
Parameter
-6.5
Min. Max.
-7.5
Min. Max.
-8.5
Min. Max.
Unit Note
Clock
tKHKH Clock cycle time
7.5 - -8.5 - 10 - ns
tKF Clock frequency
- 133 - 117 - 100 MHz
tKHKL Clock HIGH time
2.5 - 2.8 - 3.0 - ns
tKLKH Clock LOW time
2.5 - 2.8 - 3.0 - ns
Output Times
tKHQV Clock to output valid
- 6.5 - 7.5 - 8.5 ns
tKHQX Clock to output invalid
3.0 - 3.0 - 3.0 - ns
tKHQX1 Clock to output in Low-Z
2.5 - 2.5 - 2.5 - ns 1,2,3
tKHQZ Clock to output in High-Z
1.5 3.8 1.5 4.0 1.5 5.0 ns 1,2,3
tGLQV OE to output valid
- 3.5 - 3.5 - 4.0 ns 4
tGLQX OE to output in Low-Z
0 - 0 - 0 - ns 1,2,3
tGHQZ OE to output in High-Z
- 3.5 - 3.5 - 4.0 ns 1,2,3
Setup Times
tAVKH
tEVKH
Address
Clock enable ( CEN)
1.5 - 2.0 - 2.0 - ns 5
1.5 - 2.0 - 2.0 - ns 5
tCVKH Control signals
1.5 - 2.0 - 2.0 - ns 5
tDVKH Data-in
1.5 - 2.0 - 2.0 - ns 5
Hold Times
tKHAX
tKHEX
Address
Clock enable ( CEN)
0.5 - 0.5 - 0.5 - ns 5
0.5 - 0.5 - 0.5 - ns 5
tKHCX Control signals
0.5 - 0.5 - 0.5 - ns 5
tKHDX Data-in
0.5 - 0.5 - 0.5 - ns 5
Notes: 1. This parameter is sampled.
2. Output loading is specified with C1=5pF as in Figure 2.
3. Transition is measured ±200mV from steady state voltage.
4. OE can be considered a “Don’t Care” during WRITE; however, controlling OE can help fine-tune a system for
turnaround timing.
5. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of
CLK when ADV/LD is LOW and chip enabled. All other synchronous inputs meet the setup and hold times with
stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each
rising edge of CLK (when ADV/LD is LOW) to remain enabled.
PRELIMINARY (September, 2004, Version 0.0)
12
AMIC Technology, Corp.

12 Page





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