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PDF ADP3158 Data sheet ( Hoja de datos )
| Número de pieza | ADP3158 | |
| Descripción | (ADP3158 / ADP3178) 4-Bit Programmable Synchronous Buck Controllers | |
| Fabricantes | Analog Devices | |
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a
FEATURES
Optimally Compensated Active Voltage Positioning
with Gain and Offset Adjustment (ADOPT™) for
Superior Load Transient Response
Complies with VRM Specifications with Lowest
System Cost
4-Bit Digitally Programmable 1.3 V to 2.05 V Output
N-Channel Synchronous Buck Driver
Total Accuracy ؎0.8% Over Temperature
Two On-Board Linear Regulator Controllers Designed
to Meet System Power Sequencing Requirements
High Efficiency Current-Mode Operation
Short Circuit Protection for Switching Regulator
Overvoltage Protection Crowbar Protects Micro-
processors with No Additional External Components
APPLICATIONS
Core Supply Voltage Generation for:
Intel Pentium® III
Intel Celeron™
4-Bit Programmable
Synchronous Buck Controllers
ADP3158/ADP3178
FUNCTIONAL BLOCK DIAGRAM
VCC
UVLO
& BIAS
CT
ADP3158/ ADP3178
OSCILLATOR
PWM
DRIVE
REFERENCE REF
DRVH
DRVL
GND
LRFB1
VLR1
LRDRV1
LRFB2
VLR2
LRDRV2
COMP
REF
DAC+20%
CMP
–+
CS–
CS+
gm
VID DAC
VID3 VID2 VID1 VID0
GENERAL DESCRIPTION
The ADP3158 and ADP3178 are highly efficient synchronous
buck switching regulator controllers optimized for converting a
5 V main supply into the core supply voltage required by high-
performance processors. These devices use an internal 4-bit DAC
to read a voltage identification (VID) code directly from the
processor, which is used to set the output voltage between 1.3 V
and 2.05 V. They use a current mode, constant off-time archi-
tecture to drive two N-channel MOSFETs at a programmable
switching frequency that can be optimized for regulator size and
efficiency.
The ADP3158 and ADP3178 also use a unique supplemental
regulation technique called Analog Devices Optimal Positioning
Technology (ADOPT) to enhance load transient performance.
Active voltage positioning results in a dc/dc converter that
meets the stringent output voltage specifications for high-
performance processors, with the minimum number of output
capacitors and smallest footprint. Unlike voltage-mode and
standard current-mode architectures, active voltage positioning
adjusts the output voltage as a function of the load current so it
is always optimally positioned for a system transient. They also
provide accurate and reliable short circuit protection and
adjustable current limiting. The devices include an integrated
overvoltage crowbar function to protect the microprocessor
from destruction in case the core supply exceeds the nominal
programmed voltage by more than 20%.
The ADP3158 and ADP3178 contain two linear regulator
controllers that are designed to drive external N-channel
MOSFETs. The outputs are internally fixed at 2.5 V and 1.8 V
in the ADP3158, while the ADP3178 provides adjustable out-
puts that are set using an external resistor divider. These
linear regulators are used to generate the auxiliary voltages
(AGP, GTL, etc.) required in most motherboard designs,
and have been designed to provide a high bandwidth load-
transient response.
The ADP3158 and ADP3178 are specified over the commercial
temperature range of 0°C to 70°C and are available in a 16-lead
SOIC package.
ADOPT is a trademark of Analog Devices, Inc.
Pentium is a registered trademark of Intel Corporation.
Celeron is a trademark of Intel Corporation.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
ADP3158/ADP3178
4-BIT CODE
VCS–
ADP3158/
ADP3178
1 VID0
GND 16
2 VID1
DRVH 15
3 VID2
DRVL 14
4 VID3
VCC 13
5 LRFB1
LRFB2 12
6 LRDRV1 LRDRV2 11
7 CS–
COMP 10
8 CS+
CT 9
1.2V
+
1F
12V
100nF
AD820
+
100⍀
100nF
Figure 1. Closed Loop Output Voltage Accuracy
Test Circuit
VLR1
10nF
ADP3158/
ADP3178
1 VID0
GND 16
2 VID1
DRVH 15
3 VID2
DRVL 14
4 VID3
VCC 13
5 LRFB1
LRFB2 12
6 LRDRV1 LRDRV2 11
7 CS–
COMP 10
8 CS+
CT 9
+
1F
VCC
100nF
VLR2
10nF
Figure 2. Linear Regulator Output Voltage Accuracy
Test Circuit
THEORY OF OPERATION
The ADP3158 and ADP3178 use a current-mode, constant off-
time control technique to switch a pair of external N-channel
MOSFETs in a synchronous buck topology. Constant off-time
operation offers several performance advantages, including that
no slope compensation is required for stable operation. A unique
feature of the constant off-time control technique is that since
the off-time is fixed, the converter’s switching frequency is a
function of the ratio of input voltage to output voltage. The
fixed off-time is programmed by the value of an external capaci-
tor connected to the CT pin. The on-time varies in such a way
that a regulated output voltage is maintained as described below
in the cycle-by-cycle operation. The on-time does not vary under
fixed input supply conditions, and it varies only slightly as a
function of load. This means that the switching frequency remains
fairly constant in a standard computer application.
Active Voltage Positioning
The output voltage is sensed at the CS– pin. A voltage error
amplifier, (gm), amplifies the difference between the output
voltage and a programmable reference voltage. The reference
voltage is programmed to between 1.3 V and 2.05 V by an inter-
nal 4-bit DAC that reads the code at the voltage identification
(VID) pins. (Refer to Table I for output voltage vs. VID pin code
information.) A unique supplemental regulation technique called
Analog Devices Optimal Positioning Technology (ADOPT)
adjusts the output voltage as a function of the load current so it
is always optimally positioned for a load transient. Standard
(passive) voltage positioning, sometimes recommended for use
with other architectures, has poor dynamic performance which
renders it ineffective under the stringent repetitive transient
conditions specified in Intel VRM documents. Consequently,
such techniques do not allow the minimum possible number of
output capacitors to be used. ADOPT, as used in the ADP3158
and ADP3178, provides a bandwidth for transient response that
is limited only by parasitic output inductance. This yields opti-
mal load transient response with the minimum number of output
capacitors.
Cycle-by-Cycle Operation
During normal operation (when the output voltage is regulated),
the voltage error amplifier and the current comparator are the
main control elements. During the on-time of the high-side
MOSFET, the current comparator monitors the voltage between
the CS+ and CS– pins. When the voltage level between the two
pins reaches the threshold level, the DRVH output is switched
to ground, which turns off the high-side MOSFET. The timing
capacitor CT is then charged at a rate determined by the off-
time controller. While the timing capacitor is charging, the DRVL
output goes high, turning on the low-side MOSFET. When the
voltage level on the timing capacitor has charged to the upper
threshold voltage level, a comparator resets a latch. The output
of the latch forces the low-side drive output to go low and the
high-side drive output to go high. As a result, the low-side switch
is turned off and the high-side switch is turned on. The sequence
is then repeated. As the load current increases, the output voltage
starts to decrease. This causes an increase in the output of the
voltage-error amplifier, which, in turn, leads to an increase in
the current comparator threshold, thus tracking the load cur-
rent. To prevent cross conduction of the external MOSFETs,
feedback is incorporated to sense the state of the driver output
pins. Before the low-side drive output can go high, the high-side
drive output must be low. Likewise, the high-side drive output is
unable to go high while the low-side drive output is high.
Output Crowbar
An added feature of using an N-channel MOSFET as the syn-
chronous switch is the ability to crowbar the output with the
same MOSFET. If the output voltage is 20% greater than the
targeted value, the controller IC will turn on the lower MOSFET,
which will current-limit the source power supply or blow its fuse,
pull down the output voltage, and thus save the microprocessor
from destruction. The crowbar function releases at approxi-
mately 50% of the nominal output voltage. For example, if the
output is programmed to 1.5 V, but is pulled up to 1.85 V or
above, the crowbar will turn on the lower MOSFET. If in this
case the output is pulled down to less than 0.75 V, the crowbar
will release, allowing the output voltage to recover to 1.5 V if
the fault condition has been removed.
On-board Linear Regulator Controllers
The ADP3158 and ADP3178 include two linear regulator con-
trollers to provide a low cost solution for generating additional
supply rails. In the ADP3158, these regulators are internally set
to 2.5 V (LR1) and 1.8 V (LR2) with ± 2.5% accuracy. The
ADP3178 is designed to allow the outputs to be set externally
using a resistor divider. The output voltage is sensed by the high
input impedance LRFB(x) pin and compared to an internal
fixed reference.
The LRDRV(x) pin controls the gate of an external N-channel
MOSFET resulting in a negative feedback loop. The only addi-
tional components required are a capacitor and resistor for
stability. The maximum output load current is determined by
the size and thermal impedance of the external power MOSFET
that is placed in series with the supply.
REV. A
–5–
5 Page 
ADP3158/ADP3178
100
90
80
70
60
50
40
30
20
10
0
0 2 4 6 8 10 12 14 16 18 20
OUTPUT CURRENT – A
Figure 5. Efficiency vs. Load Current of the Circuit
of Figure 3
To correctly implement active voltage positioning, the low fre-
quency output impedance (i.e., the output resistance) of the
converter should be made equal to the maximum ESR of the
output capacitor array. This can be achieved by having a single-
pole roll-off of the voltage gain of the gm error amplifier, where
the pole frequency coincides with the ESR zero of the output
capacitor. A gain with single-pole roll-off requires that the gm
amplifier output pin be terminated by the parallel combination
of a resistor and capacitor. The required resistor value can be
calculated from the equation:
RCOMP
=
ROGM
ROGM
× RTOTAL
– RTOTAL
= 1 MΩ × 9.1 kΩ
1 MΩ – 9.1 kΩ
= 9.2 kΩ
where:
RTOTAL
=
nI × RSENSE
gm × RE ( MAX )
=
25 × 4 mΩ
2.2 mmho × 5 mΩ
= 9.1 kΩ
(24)
(25)
In Equations 24 and 25, ROGM is the internal resistance of the gm
amplifier, nI is the division ratio from the output voltage to
signal of the gm amplifier to the PWM comparator, and gm is the
transconductance of the gm amplifier itself.
Although a single termination resistor equal to RCOMP would yield
the proper voltage positioning gain, the dc biasing of that resistor
would determine how the regulation band is centered (i.e., offset).
Note that sometimes the specified regulation band is asymmetrical
with respect to the nominal VID voltage. With the ADP3158 and
ADP3178, the offset is already considered part of the design
procedure—no special provision is required. To accomplish the dc
biasing, it is simplest to use two resistors to terminate the gm
amplifier output, with the lower resistor (RB) tied to ground and
the upper resistor (RA) to the 12 V supply of the IC. The values of
these resistors can be calculated using:
RA
=
gm
VDIV
× (VOUT (OS )
+
K)
=
12V
2.2 mmho × (22 mV
+ 4.7 × 10–2 )
=
79.1 kΩ
(26)
where K is a constant determined by internal characteristics of the
ADP3158 and ADP3178, peak-to-peak inductor current ripple
(IRIPPLE), and the current sampling resistor (RSENSE). K can be
calculated using Equations 28 and 29. VDIV is the resistor divider
supply voltage (e.g., the recommended 12 V supply) and VOUT(OS) is
the output voltage offset from the nominal VID-programmed value
under no load condition. This offset is given by Equation 30.
The closest 1% value for RA is 78.7 kΩ. This value is then used
to solve for RB:
RB
=
RA × RCOMP
RA – RCOMP
= 78.7 kΩ × 9.2 kΩ
78.7 kΩ – 9.2 kΩ
= 10.4 kΩ
The nearest 1% value of 10.5 kΩ was chosen for RB.
K
=
I L(RIPPLE
2
)
×
(RSENSE × nI )
gm × RTOTAL
+
gm
VGNL
× RTOTAL
–
VCC
2 × gm ROGM
(27)
(28)
K
=
3.8
2
A
×
4 mΩ × 25
2.2 mmho × 9.1 kΩ
+
1.174
2.2 mmho × 9.1 kΩ
−
12V
2 × 2.2 mmho × 130 kΩ
= 4.7 × 10–2
VGNL
= VGNL0
+
IL(RIPPLE )
× RSENSE
2
× nI
− VIN
− VVID
L
× tD
× RSENSE
×
nI
(29)
VGNL
= 1V
+
3.8
A
×
4 mΩ
2
×
25
−
5V –
1.5
1.7 V
µH
× 75 ns × 4 mΩ × 25
= 1.174V
( )VOUT (OS ) = VOUT ( MAX ) − VVID
−
RE ( MAX )
× I L( RIPPLE )
2
− VVID
× kVID
VOUT (OS )
=
40
mV
−
5
mΩ
× 3.8
2
A
− 1.7V
× 5 × 10–3
=
22
mV
(30)
Finally, the compensating capacitance is determined from the
equality of the pole frequency of the error amplifier gain and the
zero frequency of the impedance of the output capacitor:
COC
=
COUT × ESR
RTOTAL
=
5 mF × 4.8 mΩ
9.1 kΩ
= 2.6
nF
The closest standard value for COC is 2.7 nF.
(31)
REV. A
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADP3158.PDF ] | |
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