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WED2ZL361MV Schematic ( PDF Datasheet ) - White Electronic

Teilenummer WED2ZL361MV
Beschreibung Synchronous Pipeline Burst NBL SRAM
Hersteller White Electronic
Logo White Electronic Logo 




Gesamt 12 Seiten
WED2ZL361MV Datasheet, Funktion
www.DataSheet4U.com
White Electronic Designs
WED2ZL361MV
1Mx36 Synchronous Pipeline Burst NBL SRAM
FEATURES
Fast clock speed: 166, 150, 133, and 100MHz
Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and
5.0ns
Single +3.3V ± 5% power supply (VCC)
Snooze Mode for reduced-standby power
Individual Byte Write control
Clock-controlled and registered addresses, data
I/Os and control signals
Burst control (interleaved or linear burst)
Packaging:
• 119-bump BGA package
Low capacitive bus loading
This product is subject to change without notice.
DESCRIPTION
The WEDC SyncBurst — SRAM family employs high-
speed, low-power CMOS designs that are fabricated
using an advanced CMOS process. WEDC’s 32Mb
SyncBurst SRAMs integrate two 1M x 18 SRAMs into a
single BGA package to provide 1M x 36 configuration. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single-clock input (CLK). The
NBL or No Bus Latency Memory utilizes all the bandwidth
in any combination of operating cycles. Address, data
inputs, and all control signals except output enable and
linear burst order are synchronized to input clock. Burst
order control must be tied “High or Low.” Asynchronous
inputs include the sleep mode enable (ZZ). Output Enable
controls the outputs at any given time. Write cycles are
internally self-timed and initiated by the rising edge of the
clock input. This feature eliminates complex off-chip write
pulse generation and provides increased timing flexibility
for incoming signals.
FIGURE 1 – PIN CONFIGURATION
(Top View)
Block Diagram
1234567
A VCC SA SA SA SA SA VCC
B SA CE2 SA ADV# SA CE2# NC
C NC SA SA VCC SA SA NC
D DQC DQPC VSS NC VSS DQPB DQB
E DQC DQC VSS CE1# VSS DQB DQB
F VCC DQC VSS OE# VSS DQB VCC
G DQC DQC BWC# SA BWB# DQB DQB
H DQC DQC VSS WE# VSS DQB DQB
J VCC VCC NC VCC NC VCC VCC
K DQD DQD VSS CLK VSS DQA DQA
L DQD DQD BWD# NC BWA# DQA DQA
M VCC DQD VSS CKE# VSS DQA VCC
N DQD DQD VSS SA1 VSS DQA DQA
P DQD DQPD VSS SA0 VSS DQPA DQA
R NC SA LBO VCC NC SA NC
T NC NC SA SA SA NC ZZ
U VCC NC NC NC NC NC VCC
CLK
CKE#
ADV#
LBO#
CE1#
CE2
CE2#
OE#
WE#
ZZ
1M x 18
CLK
CKE#
ADV#
LBO#
CS1#
CS2
CS2#
OE#
WE#
ZZ
1M x 18
CLK
CKE#
ADV#
LBO#
CS1#
CS2
CS2#
OE#
WE#
ZZ
Address Bus
(SA0 - SA19)
DQc, DQd
DQPc, DQPd
DQa, DQb
DQPa, DQPb
DQa - DQd
DQPa - DQPd
June 2004
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






WED2ZL361MV Datasheet, Funktion
White Electronic Designs
WED2ZL361MV
SNOOZE MODE
SNOOZE MODE is a low-current, “power-down” mode in
which the device is deselected and current is reduced to
ISB2Z. The duration of SNOOZE MODE is dictated by the
length of time Z is in a HIGH state. After the device enters
SNOOZE MODE, all inputs except ZZ become gated inputs
and are ignored. ZZ is an asynchronous, active HIGH input
that causes the device to enter SNOOZE MODE.
When ZZ becomes a logic HIGH, ISB2Z is guaranteed after
the setup time tZZ is met. Any READ or WRITE operation
pending when the device enters SNOOZE MODE is not
guaranteed to complete successfully. Therefore, SNOOZE
MODE must not be initiated until valid pending operations
are completed.
Description
Current during SNOOZE MODE
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to snooze current
ZZ inactive to exit snooze current
SNOOZE MODE
Conditions
ZZ VIH
SYMBOL
ISB2Z
tZZ
tRZZ
tZZI
tRZZI
Min
2(tKC)
Max
10
2(tKC)
2(tKC)
Units
mA
ns
ns
ns
ns
Notes
1
1
1
1
CLOCK
ZZ
ISUPPLY
ALL INPUTS
(except ZZ)
Output (Q)
FIGURE 2 – SNOOZE MODE TIMING DIAGRAM
tZZ
tZZI
IISB2Z
HIGH-Z
tRZZ
tRZZI
DESELECT or READ Only
DON'T CARE
June 2004
Rev. 3
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page









WED2ZL361MV pdf, datenblatt
White Electronic Designs
WED2ZL361MV
PACKAGE DIMENSION: 119 BUMP PBGA
20.32 (0.800)
TYP
7.62 (0.300)
TYP
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1.90 (0.075)
MAX
17.00 (0.669) TYP
A1
CORNER
1.27 (0.050)
TYP
1.27 (0.050) TYP
0.711 (0.028)
MAX
NOTE: Ball attach pad for above BGA package is 620 microns in diameter. Pad is solder mask defined.
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
23.00 (0.905)
TYP
ORDERING INFORMATION
Commercial Temp Range (0°C to 70°C)
Industrial Temp Range (-40°C to +85°C)
Part Number
WED2ZL361MV35BC
WED2ZL361MV38BC
WED2ZL361MV42BC
WED2ZL361MV50BC
Configuration
1M x 36
1M x 36
1M x 36
1M x 36
tCD (ns)
3.5
3.8
4.2
5.0
Clock
(MHz)
166
150
133
100
Part Number
WED2ZL361MV35BI
WED2ZL361MV38BI
WED2ZL361MV42BI
WED2ZL361MV50BI
Configuration
1M x 36
1M x 36
1M x 36
1M x 36
tCD (ns)
3.5
3.8
4.2
5.0
Clock
(MHz)
166
150
133
100
June 2004
Rev. 3
12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 Page





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